Datasheet

register, offset 0xFC8, software can selects an alternate clock source as programmed in the Alternate
Clock Configuration (ALTCLKCFG) register, offset 0x138 in the System Control Module. The
alternate clock source options available are PIOSC, RTCOSC and LFIOSC. Refer to “System
Control” on page 230 for additional information.
Note: When the ALTCLK bit is set in the GPTMCC register to enable using the alternate clock
source, the synchronization imposes restrictions on the starting count value (down-count),
terminal value (up-count) and the match value. This restriction applies to all modes of
operation. Each event must be spaced by 4 Timer (ALTCLK) clock periods + 2 system clock
periods. If some events do not meet this requirement, then it is possible that the timer block
may need to be reset for correct functionality to be restored.
Example: ALTCLK= T
PIOSC
= 62.5ns (16Mhz Trimmed)
T
hclk
= 1us (1Mhz)
4*62.5ns + 2*1us = 2.25us 2.25us/62.5ns = 36 or 0x23
The minimum values for the periodic or one-shot with a match interrupt enabled are:
GPTMTAMATCHR = 0x23 GPTMTAILR = 0x46
16.3.3 Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 1124). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer
n Prescale (GPTMTnPR) registers, with the exception of RTC mode.
16.3.3.1 One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTM Timer n Mode (GPTMTnMR) register (see page 1125). The timer is configured to count
up or down using the TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 1133), the
timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit
is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin
counting (see “Wait-for-Trigger Mode” on page 1116). Table 16-4 on page 1107 shows the values that
are loaded into the timer registers when the timer is enabled.
Table 16-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes
Count Up ModeCount Down ModeRegister
0x0GPTMTnILRGPTMTnR
0x0GPTMTnILR in concatenated mode; GPTMTnPR in
combination with GPTMTnILR in individual mode
GPTMTnV
0x0 in individual mode; not available
in concatenated mode
GPTMTnPR in individual mode; not available in
concatenated mode
GPTMTnPS
When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start
value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is
counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional
1107December 13, 2013
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TM4C129XNCZAD Microcontroller