Datasheet

Register 44: SHA DMA Interrupt Clear (SHA_DMAIC), offset 0x01C
The SHA DMA Interrupt Clear register is used to clear the SHA_DMA_RIS and SHA_DMA_MIS
registers by writing a 1 to each register bit.
Note: This registers always reads as zero.
SHA DMA Interrupt Clear (SHA_DMAIC)
Base
Offset 0x01C
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINDINCOUTreserved
W1CW1CW1CROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
Context Out DMA Done Masked Interrupt Status
Writing a 1 to this bit clears the COUT bit in the SHA_DMA_RIS and
SHA_DMA_MIS register.
0W1CCOUT2
Data In DMA Done Interrupt Clear
Writing a 1 to this bit clears the DIN bit in the SHA_DMA_RIS and
SHA_DMA_MIS register.
0W1CDIN1
Context In DMA Done Raw Interrupt Status
Writing a 1 to this bit clears the CIN bit in the SHA_DMA_RIS and
SHA_DMA_MIS register..
0W1CCIN0
1101December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller