Datasheet

Register 43: SHA DMA Masked Interrupt Status (SHA_DMAMIS), offset 0x018
The SHA DMA Masked Interrupt Status (SHA_DMA_MIS) register displays the raw interrupts that
are unmasked in the SHA_DMA_RIS register.
SHA DMA Masked Interrupt Status (SHA_DMAMIS)
Base
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINDINCOUTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
Context Out DMA Done Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A COUT interrupt has occurred.1
0ROCOUT2
Data In DMA Done Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A DIN interrupt has occurred.1
0RODIN1
Context In DMA Done Raw Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
A CIN interrupt has occurred.1
0ROCIN0
December 13, 20131100
Texas Instruments-Advance Information
SHA/MD5 Accelerator