Datasheet

Register 40: SHA Interrupt Enable (SHA_IRQENABLE), offset 0x11C
The SHA_IRQENABLE register contains an enable bit for each unique interrupt. An interrupt is
enabled when both the global enable, the IT_EN bit, in the SHA_SYSCONFIG register and the bit
in this register are both set to 1.
SHA Interrupt Enable (SHA_IRQENABLE)
Base 0x4403.4000
Offset 0x11C
Type RW, reset 0x0000.0007
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
M_OUTPUT_READY
M_INPUT_READY
reserved
M_CONTEXT_READY
reserved
RWRWRORWROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Mask for context ready interrupt
DescriptionValue
Context ready interrupt is disabled (masked).0
Context ready interrupt is enabled.1
0RWM_CONTEXT_READY3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
Mask for input ready interrupt
DescriptionValue
Input ready interrupt is disabled (masked).0
Input ready interrupt is enabled.1
1RWM_INPUT_READY1
Mask for output ready interrupt
DescriptionValue
Output ready interrupt is disabled (masked).0
Output ready interrupt is enabled.1
1RWM_OUTPUT_READY0
December 13, 20131096
Texas Instruments-Advance Information
SHA/MD5 Accelerator