Datasheet

Register 39: SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118
Interrupt Status Register
SHA Interrupt Status (SHA_IRQSTATUS)
Base 0x4403.4000
Offset 0x118
Type RO, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
OUTPUT_READY
INPUT_READY
reserved
CONTEXT_READY
reserved
ROROROROROROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Context Ready Status
DescriptionValue
The context registers are not available for a new context.0
The context input registers are available for a new context for
the next packet to be processed.
1
1ROCONTEXT_READY3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2
Input Ready Status
DescriptionValue
The Data FIFO is not ready to receive the next 64-byte data
block.
0
The Data FIFO (SHA_DATA_n_IN registers) is ready to receive
the next 64-byte data block.
1
0ROINPUT_READY1
Output Ready Status
DescriptionValue
No saved context available.0
A saved context is available from the context output registers.1
0ROOUTPUT_READY0
1095December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller