Datasheet

This register is written with the initial digest count and can be read to determine the digest count

result. Note that for Initial Digest Count writes, bits 5:0 must be zero. This register is written the

initial digest byte count when both the HMAC_KEY_PROC bit and the ALGO_CONSTANT bit is zero in

the SHA_MODE register. When either the HMAC_KEY_PROC bit or the ALGO_CONSTANT bit is 1,

this register does not need to be written because it is overwritten with 64 or 0 automatically. When

starting an HMAC operation from precomputes (HMAC_KEY_PROC=0), the value 64 must be written

in the SHA_DIGESTCOUNT register. Note that the value written should always be a 64 byte multiple,

the lower 6 bits written are ignored. The updated digest byte count (initial digest byte count + bytes

processed) can be read from this register when the status register indicates that the operation is

done or when a µDMA context out is requested.

SHA Digest Count (SHA_DIGEST_COUNT)

Base 0x4403.4000

Offset 0x040

Type RW, reset 0x0000.0000

16171819202122232425262728293031

COUNT

RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType

0000000000000000Reset

0123456789101112131415

COUNT

RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Digest Count

This field is written with the initial digest value for bits [31:6] only ([5:0]

are assumed to be zeros).

When read, this outputs the result/intermediate digest count.

0x0000.0000RWCOUNT31:0

December 13, 20131086

Texas Instruments-Advance Information

SHA/MD5 Accelerator