Datasheet

Figure 15-3. SHA/MD5 Interrupt Subroutine
Enter ISR
Exit ISR
Read the status register to determine the
type of the generated interrupt
value = SHA_S_IRQSTATUS
Is the interrupt caused by
input buffer ready event?
SHA_S_IRQSTATUS[1]
INPUT_READY == 1
Write the next 64-byte data
block SHA_S_DATA_i_IN[31:0]
DATA_i_IN = 0x-
Read the result
result = SHA_S_ODIGEST_A
(to H for SHA-1)
Is the interrupt caused by
result ready/context available event?
SHA_S_IRQSTATUS[1]
OUTPUT_READY == 1
Is the interrupt caused by
context input ready event?
SHA_S_IRQSTATUS[3]
CONTEXT_READY == 1
Write the new context
SHA_S_IDIGEST_i[31:0] DATA = 0x-
SHA_S_ODIGEST_i[31:0] DATA = 0x-
SHA_S_DIGEST_COUNT[31:0] COUNT = 0x-
SHA_S_LENGTH[31:0] LENGTH = 0x-
Read the context
context1 = SHA_S_IDIGEST_i[31:0] DATA
context2 = SHA_S_DIGEST_COUNT[31:0] COUNT
conetxt3 = SHA_S_LENGTH[31:0] LENGTH
noyes
yes
no
no
yes
15.2 SHA/MD5 Register Map
Table 15-12 on page 1081 lists the SHA/MD5 registers. The SHA Module comprises registers that
exist at an offset relative to the SHA/MD5 Module base address and a small set of SHA/MD5 µDMA
interrupt registers that exist at an offset relative to an CRC and Cryptographic Modules base address.
The SHA/MD5 Module register offsets are relative to the base address 0x4403.4000. The SHA
µDMA offsets are relative to the base address 0x4403.0000 .
Table 15-12. SHA/MD5 Register Map
See
page
DescriptionResetTypeNameOffset
SHA/MD5 Module Registers (SHA/MD5 Module Offset)
1085SHA Outer Digest A0x0000.0000RWSHA_ODIGEST_A0x000
1085SHA Outer Digest B0x0000.0000RWSHA_ODIGEST_B0x004
1085SHA Outer Digest C0x0000.0000RWSHA_ODIGEST_C0x008
1085SHA Outer Digest D0x0000.0000RWSHA_ODIGEST_D0x00C
1081December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller