Datasheet

Table 15-9. SHA-1 Apply on the Key
ValueRegister/Bit Field/Programming ModelStep
-SHA_DATA_n_IN (i = 0 to 15)Load the first part of the key. (Here, the key is like a
message.)
0x1SHA_MODE[2:1] ALGOSelect the SHA-1 hash function.
0x1SHA_MODE[3] ALGO_CONSTANTSelect a new hash operation.
0x1SHA_MODE[4] CLOSE_HASHClose the hash; the key is processed in single pass.
Operational Modes Configuration
SHA/MD5 Polling Mode
Figure 15-2 on page 1079 shows the SHA/MD5 polling mode. SHA/MD5 polling mode uses the following
registers: SHA_IRQSTATUS, SHA_DATA_n_IN, SHA_ODIGEST_A, SHA_DIGEST_COUNT, and
SHA_LENGTH.
Figure 15-2. SHA/MD5 Polling Mode
START
Write the next 64-byte data block
SHA_S_DATA_i_IN[31:0] = 0x-
END
no
yes
no
Is the input buffer ready
to receive the next 64-byte data block?
SHA_S_IRQSTATUS[1] INPUT_READY
== 1
yes
Intermediate result ready?
SHA_S_IRQSTATUS[0]
OUTPUT_READY == 1
Are there more 64-byte
data blocks to be processed?
SHA_S_DIGEST_COUNT[31:0] COUNT
< SHA_S_LENGTH[31:0] LENGTH
Read the result
result = SHA_S_DIGEST_A to
SHA_S_DIGEST_E (for SHA-1)
no
yes
SHA/MD5 Interrupt Mode
The procedure in configures the SHA/MD5 module to work in interrupt-based mode. (For the interrupt
subroutine, see the Interrupt Servicing section.)
Table 15-10. Interrupt Mode
ValueRegister/Bit Field/Programming ModelStep
0x1SHA_SYSCONFIG[2] IT_ENEnable the interrupt request to the Cortex-A8 MPU INTC.
1079December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller