Datasheet

Closing a Hash
The amount of data to hash is not necessarily a multiple of 64 bytes. In this case, the CLOSE_HASH
bit in the SHA_MODE register must be set to append padding so that the message size becomes
a multiple of 64 bytes. See the previous MD5 algorithm for more information on padding.
The module is fed with a 64-byte block of data, as long as enough data is available. However, a
pad is appended on the last block of data. This can result in the creation of an extra 64-byte block.
The one or two last blocks that contain the padding are processed the same way as the other blocks.
Hash completion is then indicated the same way as for a new hash, and the 128-bit result can be
read in the digest registers. The SHA_DIGESTCOUNT register returns restored digest count and
length when it is read, and hashing completes.
15.1.5.3 Generating an Software Interrupt
If the IT_EN bit is 1 in the SHA_SYSCONFIG register, an interrupt is generated at the completion
of the hash by the following steps:
1. Receive last block of data (= 64 bytes). (The number of data bytes defined by the SHA_LENGTH
register is received in the digest registers, from SHA_ODIGEST_A/SHA_IDIGEST_A to
SHA_ODIGEST_H/SHA_IDIGEST_H.
2. If required, apply padding to the last block of data.
3. Hash the last block of data (80 cycles in SHA-1 mode and 64 cycles in MD5, SHA-224, and
SHA-256 modes).
4. If required, add an extra 64-byte block of data to complete the padding.
5. Hash this extra block of data (80 cycles in SHA-1 mode and 64 cycles in MD5, SHA-224, and
SHA-256 modes).
6. An interrupt is generated (active low).
15.1.6 SHA/MD5 Performance Information
The following table lists the performance for all supported key sizes and modes of operations. It
assumed that the engine is kept fully utilized (that is, the host is supplying input block and retrieving
output blocks in such a way, that the engine never has to wait for input) and that the previous output
has been retrieved before the next output is ready.
Maximum throughput does not include per operation overhead cycles, as the impact on the throughput
depends on the size of the block being processed, and would be negligible for large blocks anyway.
Table 15-7. SHA/MD5 Performance
Cycles per blockCycles per operationAlgorithmOperation
650 / 65MD5
Hash
810 / 81SHA-1
650 / 65SHA-224
650 / 65SHA-256
December 13, 20131076
Texas Instruments-Advance Information
SHA/MD5 Accelerator