Datasheet

Register 20: DES DMA Raw Interrupt Status (DES_DMARIS), offset 0x034
The DES DMA Raw Interrupt Status register contains the raw interrupt status. If any of these bits
read 1, the processor is interrupted if the corresponding masked interrupt status bit is set to 1.
DES DMA Raw Interrupt Status (DES_DMARIS)
Base 0x4403.0000
Offset 0x034
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINDINDOUTreserved
RWRWRWROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
Data Out DMA Done Raw Interrupt Status
DescriptionValue
No Interrupt.0
The µDMA has written the last word of the process result and
an interrupt has been triggered and is pending.
1
0RWDOUT2
Data In DMA Done Raw Interrupt Status
DescriptionValue
No Interrupt.0
The µDMA has written the last word of input data to the internal
FIFO of the engine and an interrupt has been triggered and is
pending.
1
0RWDIN1
Context In DMA Done Raw Interrupt Status
DescriptionValue
No interrupt.0
The µDMA has completed a context write to the internal register
and an interrupt has been triggered and is pending.
1
0RWCIN0
December 13, 20131064
Texas Instruments-Advance Information
Data Encryption Standard Accelerator (DES)