Datasheet

The first option provides highest level of security; the last option is compatible with single DES. See
Table 14-1 on page 1039 for key use.
Table 14-1. Key Repartition
Key3_HKey3_LKey2_HKey2_LKey1_HKey1_LMode
XXXX√√64-bit (DES)
√√√√√√192-bit (3DES)
ECB, CBC, and CFB modes can be used with DES and 3DES modes.
14.2 DES Block Diagram
The module architecture consists of primary blocks, as shown in Figure 14-1 on page 1039. The DES
module includes a register interface, and a µDMA and interrupt interface.
Depending of the availability of context and data, the DES engine is automatically triggered to
process the data. The DES engine is directly connected to the context and data registers such that
it can immediately start processing when all data is available.
Packets (blocks of 64 bits) must be parsed into blocks and sequentially fed into the DES, which can
buffer the block currently being processed as well as an additional block that may be queued in
advance.
Figure 14-1. DES Block Diagram
DES Cipher Core
Mode
Control
FSM
DES
Feedback
Mode
cotnrol
Context
Registers
I/O Control FSM/ DMA Requests
14.2.1 µDMA Control
The µDMA and interrupt request logic is controlled by the DES Engine. The DES Engine can have
multiple µDMA request signals active in parallel.
There are three DMA channels available:
1039December 13, 2013
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TM4C129XNCZAD Microcontroller