Datasheet

Register 40: AES DMA Raw Interrupt Status (AES_DMARIS), offset 0x024
The AES DMA Raw Interrupt Status (AES_DMARIS) register contains the raw interrupt status. If
any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status
bit is set to '1.'
AES DMA Raw Interrupt Status (AES_DMARIS)
Base 0x4403.0000
Offset 0x024
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINCOUTDINDOUTreserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Data Out DMA Done Raw Interrupt Status
DescriptionValue
No Interrupt.0
The µDMA has written the last word of the process result and
an interrupt has been triggered and is pending.
1
0RWDOUT3
Data In DMA Done Raw Interrupt Status
DescriptionValue
No Interrupt.0
The µDMA has written the last word of input data to the internal
FIFO of the engine and an interrupt has been triggered and is
pending.
1
0RWDIN2
Context Out DMA Done Raw Interrupt Status
DescriptionValue
No Interrupt.0
The µDMA has completed the output context read from the
internal register and an interrupt has been triggered and is
pending.
1
0RWCOUT1
December 13, 20131034
Texas Instruments-Advance Information
Advance Encryption Standard Accelerator (AES)