Datasheet

Register 39: AES DMA Interrupt Mask (AES_DMAIM), offset 0x020
The AES DMA Interrupt Mask (AES_DMAIM) register controls interrupt behavior and is used to
program which interrupts are suppressed.
AES DMA Interrupt Mask (AES_DMAIM)
Base 0x4403.0000
Offset 0x020
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CINCOUTDINDOUTreserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Data Out DMA Done Interrupt Mask
If this bit is unmasked, an interrupt is generated when the µDMA writes
the last word of the process result.
DescriptionValue
The DOUT interrupt is suppressed and not sent to the interrupt
controller.
0
The DOUT interrupt is sent to the interrupt controller.1
0RWDOUT3
Data In DMA Done Interrupt Mask
If this bit is unmasked, an interrupt is generated when the µDMA writes
the last word of input data to the internal FIFO of the engine.
DescriptionValue
The DIN interrupt is suppressed and not sent to the interrupt
controller.
0
The DIN interrupt is sent to the interrupt controller.1
0RWDIN2
Context Out DMA Done Interrupt Mask
If this bit is unmasked, an interrupt is generated when the µDMA
completes the output context read from the internal register.
DescriptionValue
The COUT interrupt is suppressed and not sent to the interrupt
controller.
0
The COUT interrupt is sent to the interrupt controller.1
0RWCOUT1
December 13, 20131032
Texas Instruments-Advance Information
Advance Encryption Standard Accelerator (AES)