Datasheet

Register 37: AES Interrupt Enable (AES_IRQENABLE), offset 0x090
This register contains an enable bit for each unique interrupt generated by the module. It matches
the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set
to 1. An interrupt that is enabled is propagated to the NVIC controller. All AES software interrupts
need to be enabled explicitly by writing this register.
Note: If the application uses Interrupt Mode, an interrupt is generated for each block of processed
data. To support larger data flow, AES µDMA Mode should be used and the bits in the
AES_IRQENABLE register should be cleared.
AES Interrupt Enable (AES_IRQENABLE)
Base 0x4403.6000
Offset 0x090
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CONTEXT_IN
DATA_IN
DATA_OUT
CONTEXT_OUT
reserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
Context Out Interrupt Enable
DescriptionValue
Authentication tag (and IV) interrupt(s) is/are disabled.0
Authentication tag (and IV) interrupt(s) is/are enabled.1
0RWCONTEXT_OUT3
Data Out Interrupt Enable
DescriptionValue
The data out interrupt is disabled.0
The data out interrupt is enabled.1
0RWDATA_OUT2
Data In Interrupt Enable
DescriptionValue
The data in interrupt is disabled.0
The data in interrupt is enabled.1
0RWDATA_IN1
1029December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller