Datasheet

Register 36: AES Interrupt Status (AES_IRQSTATUS), offset 0x08C
This register indicates the interrupt status. If one of the interrupt bits is set, the interrupt output is
asserted.
AES Interrupt Status (AES_IRQSTATUS)
Base 0x4403.6000
Offset 0x08C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CONTEXT_IN
DATA_IN
DATA_OUT
CONTEXT_OUT
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
Context Output Interrupt Status
DescriptionValue
Authentication tag (and IV) interrupt(s) is/are not active.0
Authentication tag (and IV) interrupt(s) is/are active and the
interrupt output has been triggered.
1
0ROCONTEXT_OUT3
Data Out Interrupt Status
DescriptionValue
The data out interrupt is not active.0
The data out interrupt is active and the interrupt output has been
triggered.
1
0RODATA_OUT2
Data In Interrupt Status
DescriptionValue
The data in interrupt is not active.0
The data in interrupt is active and the interrupt output has been
triggered.
1
0RODATA_IN1
1027December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller