Datasheet

Register 25: AES Data RW Plaintext/Ciphertext 0 (AES_DATA_IN_0), offset
0x060
Register 26: AES Data RW Plaintext/Ciphertext 1 (AES_DATA_IN_1), offset
0x064
Register 27: AES Data RW Plaintext/Ciphertext 2 (AES_DATA_IN_2), offset
0x068
Register 28: AES Data RW Plaintext/Ciphertext 3 (AES_DATA_IN_3), offset
0x06C
The AES Data RW Plaintext/Ciphertext n (AES_DATA_IN_n) registers are used to read and write
plaintext/ciphertext. The AES_DATA_IN_0 register contains the most significant word; the
AES_DATA_IN_3 register contains least significant word.
Note: The AES_DATA_IN_0 register acts as a FIFO and shifts data into the other
AES_DATA_IN_n registers.
AES Data RW Plaintext/Ciphertext (AES_DATA_IN_n)
Base 0x4403.6000
Offset 0x060
Type RW, reset 0x0000.0000
16171819202122232425262728293031
DATA
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
DATA
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Secure Data RW Plaintext/Ciphertext
This field holds the plaintext/ciphertext data.
0x00000000RWDATA31:0
December 13, 20131020
Texas Instruments-Advance Information
Advance Encryption Standard Accelerator (AES)