Datasheet

Register 21: AES Control (AES_CTRL), offset 0x050
This register determines the mode of operation of the AES Engine.
AES Control (AES_CTRL)
Base 0x4403.6000
Offset 0x050
Type RW, reset 0x8000.0000
16171819202122232425262728293031
GCMCCMCCM_LCCM_Mreserved
SAVE_CONTEXT
SVCTXTRDY
CTXTRDY
RWRWRWRWRWRWRWRWRWRRRRRWROROType
0000000000000001Reset
0123456789101112131415
OUTPUT_READY
INPUT_READY
DIRECTION
KEY_SIZEMODECTRCTR_WIDTHICMCFBXTSF8F9CBCMAC
RORORWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Context Data Registers Ready
DescriptionValue
The context data registers are not ready to be overwritten.0
The context data registers can be overwritten and the host is
permitted to write the next context.
1
1ROCTXTRDY31
AES TAG/IV Block(s) Ready
Note: This bit is only asserted if the SAVE_CONTEXT bit is set to 1.
This bit is mutual exclusive with the CTXTRDY bit.
DescriptionValue
AES authentication TAG and/or IV block(s) is/are not available.0
Indicates the AES authentication TAG and /or IV block(s) is/are
available for the host to retrieve.
1
0ROSVCTXTRDY30
TAG or Result IV Save
If this bit is set, the CONTEXT_OUT interrupt bit is set in the
AES_IRQSTATUS register if the operation is finished and related signals
are enabled.
DescriptionValue
No effect.0
Indicates an authentication TAG of result IV needs to be stored
as a result context.
1
0RWSAVE_CONTEXT29
1013December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller