Datasheet

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PIN CONFIGURATION
TopView TQFP
36
35
34
33
32
31
30
29
28
27
26
25
SYNC
BLS
AESOUT
VDD33
TX+
TX-
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
BCKB LRCKB SDINB SDOUTB BGND DGND3 VIO NC SDOUT
A
SDINA LRCKA BCKA
RXCKI
NC
NC
DGND1
VDD18
CPM
CS/A0
CCLK/SCL
CDIN/A1
CDOUT/SDA
INT
RST
1
2
3
4
5
6
7
8
9
10
11
12
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
AGND
LOCK
RXCKO
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
DIX4192
NC=NoConnection
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
PIN DESCRIPTIONS
NAME PIN NUMBER I/O DESCRIPTION
RX1+ 1 Input Line receiver 1, noninverting input
RX1– 2 Input Line receiver 1, inverting input
RX2+ 3 Input Line receiver 2, noninverting input
RX2– 4 Input Line receiver 2, inverting input
RX3+ 5 Input Line receiver 3, noninverting input
RX3– 6 Input Line receiver 3, inverting input
RX4+ 7 Input Line receiver 4, noninverting input
RX4– 8 Input Line receiver 4, inverting input
VCC 9 Power DIR comparator and PLL power supply, +3.3V nominal
AGND 10 Ground DIR comparator and PLL power-supply ground
LOCK 11 Output DIR PLL lock flag (active low)
RXCKO 12 Output DIR recovered master clock (tri-state output)
RXCKI 13 Input DIR reference clock
NC 14, 15, 41 — No internal signal connection, internally bonded to ESD pad
DGND1 16 Ground Digital core ground
VDD18 17 Power Digital core supply, +1.8V nominal
CPM 18 Input
Control port mode, 0 = SPI mode, 1 = I
2
C mode
CS or A0 19 Input
Chip select (active low) for SPI mode or programmable slave address for I
2
C mode
CCLK or SCL 20 Input
Serial data clock for SPI mode or I
2
C mode
CDIN or A1 21 Input
SPI port serial data input or programmable slave address for I
2
C mode
CDOUT or SDA 22 I/O
SPI port serial data output (tri-state output) or serial data I/O for I
2
C mode
8
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