Datasheet

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ELECTRICAL CHARACTERISTICS: I
2
C Standard and Fast Modes
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
All specifications are at T
A
= +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
DIX4192
PARAMETER CONDITIONS MIN TYP MAX UNITS
HOST INTERFACE: I
2
C Standard Mode
(1)
SCL clock frequency, f
SCL
0 100 kHz
Hold time repeated START condition, t
HDSTA
4 µ s
Low period of SCL clock, t
LOW
4.7 µ s
High period of SCL clock, t
HIGH
4 µ s
Setup time repeated START condition, t
SUSTA
4.7 µ s
Data hold time, t
HDDAT
0
(2)
3.45
(3)
µ s
Data setup time, t
SUDAT
250 ns
Rise time for Both SDA and SDL, t
R
1000 ns
Fall time for Both SDA and SDL, t
F
300 ns
Setup time for STOP condition, t
SUSTO
4 µ s
Bus free time between START and STOP, t
BUF
4.7 µ s
Capacitive load for each bus Line, C
B
400 pF
Noise margin at low level (including hysteresis), V
NL
0.1 × VIO V
Noise margin at high level (including hysteresis), V
NH
0.2 × VIO V
HOST INTERFACE: I
2
C Fast Mode
(1)
SCL clock frequency, f
SCL
0 400 kHz
Hold time repeated START condition, t
HDSTA
0.6 µ s
Low period of SCL clock, t
LOW
1.3 µ s
High period of SCL clock, t
HIGH
0.6 µ s
Setup time repeated START condition, t
SUSTA
0.6 µ s
Data hold time, t
HDDAT
0
(2)
0.9
(3)
µ s
Data setup time, t
SUDAT
100
(4)
ns
Rise time for both SDA and SDL, t
R
20 + 0.2C
B
(5)
300 ns
Fall time for both SDA and SDL, t
F
20 + 0.2C
B
(5)
300 ns
Setup time for STOP condition, t
SUSTO
0.6 µ s
Bus free time between START and STOP, t
BUF
1.3 µ s
Spike pulse width suppressed by input filter, t
SP
0 50 ns
Capacitive load for Each bus Line, C
B
400 pF
Noise margin at low level (including hysteresis), V
NL
0.1 × VIO V
Noise margin at high level (including hysteresis), V
NH
0.2 × VIO V
(1) All values referred to the V
IH
minimum and V
IL
maximum levels listed in the Digital I/O Characteristics section of the Electrical
Characteristics: General, DIR, and DIT table.
(2) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
minimum input level) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum t
HDDAT
has only to be met if the device does not stretch the Low period (t
LOW
) of the SCL signal.
(4) A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement that t
SUDAT
be 250ns (minimum)
must then be met. For the DIX4192, this condition is automatically the case, since the device does not stretch the Low period of the SCL
signal.
(5) C
B
is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are
allowed.
5
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