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DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
Register 1D: General-Purpose Output 3 (GPO3) Control Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 GPO33 GPO32 GPO31 GPO30
GPO[33:30] General-Purpose Output 3 (GPO3) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO3.
GPO33 GPO32 GPO31 GPO30 GPO3 Function
0 0 0 0 GPO3 is forced low (default)
0 0 0 1 GPO3 is forced high
0 0 1 0 Reserved
0 0 1 1 Transmitter interrupt, active low
0 1 0 0 Receiver interrupt, active low
0 1 0 1 Receiver 50/15 µ s pre-emphasis, active low
0 1 1 0 Receiver non-audio data, active high
0 1 1 1 Receiver non-valid data, active high
1 0 0 0 Receiver channel status bit
1 0 0 1 Receiver user data bit
1 0 1 0 Receiver block start clock
Receiver COPY bit
1 0 1 1
(0 = copyright asserted, 1 = copyright not asserted)
Receiver L-bit
1 1 0 0
(0 = first generation or higher, 1 = original)
1 1 0 1 Receiver parity error, active high
1 1 1 0 Receiver internal sync clock
1 1 1 1 Transmitter internal sync clock
Register 1E: General-Purpose Output 4 (GPO4) Control Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 GPO43 GPO42 GPO41 GPO40
GPO[43:40] General-Purpose Output 4 (GPO4) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO4.
GPO43 GPO42 GPO41 GPO40 GPO4 Function
0 0 0 0 GPO4 is forced low (default)
0 0 0 1 GPO4 is forced high
0 0 1 0 Reserved
0 0 1 1 Transmitter interrupt, active low
0 1 0 0 Receiver interrupt, active low
0 1 0 1 Receiver 50/15 µ s pre-emphasis, active low
0 1 1 0 Receiver non-audio data, active high
0 1 1 1 Receiver non-valid data, active high
1 0 0 0 Receiver channel status bit
1 0 0 1 Receiver user data bit
1 0 1 0 Receiver block start clock
Receiver COPY bit
1 0 1 1
(0 = copyright asserted, 1 = copyright not asserted)
Receiver L-bit
1 1 0 0
(0 = first generation or higher, 1 = original)
1 1 0 1 Receiver parity error, active high
1 1 1 0 Receiver internal sync clock
1 1 1 1 Transmitter internal sync clock
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