Datasheet

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L R L R
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AES3BitStream
DIRSYNC
LRCK,I SFormat(input)
2
LRCK,Left-orRight-
JustifiedFormats(input)
±5% ±5%
DataSliporRepeatmayoccurwhentheLRCKedgesindicatedarewithinthe 5%window.±
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
1 Buffer transfer completed
Register 15: Receiver Status Register 3 (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 0 0 0 OSLIP
Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated.
OSLIP Receiver Output Data Slip Error Status
OSLIP Receiver OSLIP Error Status
0 No error
1 DIR output data Slip/Repeat error detected
An OSLIP interrupt is possible when the DIR output is used as the source for either the Port A or Port B audio serial port and the port is configured to operate
in slave mode. Figure 35 shows the timing associated with the OSLIP interrupt.
When only one audio serial port (Port A or Port B) is sourced by the DIR output, then the OSLIP status bit and interrupt applies to that port. If both Port A and
Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only.
Figure 35. DIR Output Slip/Repeat (OSLIP) Behavior
Register 16: Receiver Interrupt Mask Register 1
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI
MCSCRC Channel Status CRC Error Interrupt Mask
MCSCRC CRC Interrupt
0 Masked (default)
1 Enabled
MPARITY Parity Error Interrupt Mask
MPARITY Parity Error Interrupt
0 Masked (default)
1 Enabled
MVBIT Validity Error Interrupt Mask
MVBIT Validity Error Interrupt
0 Masked (default)
1 Enabled
45
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