Datasheet

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DIX4192

SBFS031C – JANUARY 2006 – REVISED JUNE 2006

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

0 0 0 0 TSLIPM1 TSLIPM0 TBTIM1 TBTIM0

TBTIM[1:0] Transmitter Buffer Transfer Interrupt Mode

These bits are utilized to select the active trigger state for the BTI interrupt.

TBTIM1 TBTIM0 Interrupt Active State

0 0 Rising edge active (default)

0 1 Falling edge active

1 0 Level active

1 1 Reserved

TSLIPM[1:0] Transmitter Data Source Slip Interrupt Mode

These bits are utilized to select the active trigger state for the TSLIP interrupt.

TSLIPM1 TSLIPM0 Interrupt Active State

0 0 Rising edge active (default)

0 1 Falling edge active

1 0 Level active

1 1 Reserved

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

0 0 0 RXBTD RXCLK 0 RXMUX1 RXMUX0

RXMUX[1:0] Receiver Input Source Selection

These bits are used to select the output of the line receiver to be used as the input data source for the DIR core.

RXMUX1 RXMUX0 Input Selection

0 0 RX1 (default)

0 1 RX2

1 0 RX3

1 1 RX4

RXCLK Receiver Reference Clock Source

This bit is used to select the reference clock source for PLL1 in the DIR core.

RXCLK Receiver Reference Clock

0 RXCKI (default)

1 MCLK

RXBTD Receiver C and U Data Buffer Transfer Disable

This bit is used to enable and disable buffer transfers between the Receiver Access (RA) and User Access (UA) buffers for both channel

status (C) and user (U) data.

Buffer transfers are typically disabled to allow the customer to read C and U data from the DIR UA buffer via the SPI or I

C serial host

interface. Once read, the RA-to-UA buffer transfer can be re-enabled to allow the RA buffer to update the contents of the UA buffer in real

time.

RXBTD Receiver Access (RA) to User Access (UA) Buffer Transfers

0 Enabled (default)

1 Disabled; the user may read C and U data from the DIR UA buffers.

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