Datasheet

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DIX4192

SBFS031C – JANUARY 2006 – REVISED JUNE 2006

ACLK[1:0] Port A Master Clock Source

These bits are used to set the master clock source for Port A when configured for Master mode operation.

ACLK1 ACLK0 Master Clock Source

0 0 MCLK (default)

0 1 RXCKI

1 0 RXCKO

1 1 Reserved

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

0 BMUTE BOUTS1 BOUTS0 BM/S BFMT2 BFMT1 BFMT0

BFMT[2:0] Port B Audio Data Format

These bits are used to set the audio input and output data format for Port B. Refer to the Audio Serial Port Operation section for

illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable

timing diagram and parameters.

BFMT2 BFMT1 BFMT0 Audio Data Format

0 0 0 24-Bit Left-Justified (default)

0 1

24-Bit Philips I

0 1 0 Unused

0 1 1 Unused

1 0 0 16-Bit Right-Justified

1 0 1 18-Bit Right-Justified

1 1 0 20-Bit Right-Justified

1 1 1 24-Bit Right-Justified

BM/S Port B Slave/Master Mode

This bit is used to set the audio clock mode for Port B to either Slave or Master.

BM/S Slave/Master Mode

0 Slave mode; the LRCK and BCK clocks are generated by an external source. (default)

1 Master mode; the LRCK and BCK clocks are derived from the Port A master clock source.

BOUTS[1:0] Port B Output Source

These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45).

BOUTS1 BOUTS0 Output Data Source

0 0 Port B input, for data loop back. (default)

0 1 Port A input

1 0 DIR

1 1 Reserved

BMUTE Port B Output Mute

This bit is used to mute the Port B audio data output.

BMUTE Output Mute

0 Disabled; SDOUTB is driven by the output data source. (default)

1 Enabled; SDOUTB is forced low.

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