Datasheet

www.ti.com
SN74AHCT1G125
orEquivalent
+5V
5
2
1
3
4
Directtoexternallogic
operatingfromtheVIOsupply.
AESOUT
To+5VLogic
(VIOsupply=+3.0Vto+3.3V)
SN74AVC1T45
orEquivalent
IfVIO<+3.0V.
VIO
+5V
5
+3.3V
6
3
1
2
4
ToBalancedorUnbalanced
LineInterface
AESOUT
2
8
7
ToBalancedorUnbalanced
LineInterface
3
6
5
1
1
SN75ALS191
REGISTER AND DATA BUFFER ORGANIZATION
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
APPLICATIONS INFORMATION (continued)
Figure 33. CMOS/TTL Output Logic Interface
Figure 34. External Line Driver Interface
The DIX4192 organizes the on-chip registers and data buffers into four pages. The currently active page is
chosen by programming the Page Selection Register to the desired page number. The Page Selection Register
is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates
the page selection corresponding to the Page Selection Register value.
Table 2. Register Page Selection
Page Selection Register Value (Hex) Selected Register Page
00 Page 0, control and status registers
01 Page 1, DIR channel status and user data buffers
02 Page 2, DIT channel status and user data buffers
03 Page 3, reserved
Register Page 0 contains the control registers utilized to configure the various function blocks within the
DIX4192. In addition, status registers are provided for flag and error conditions, with many of the status bits
capable of generating an interrupt signal when enabled. See Table 3 for the control and status register map.
Register Page 1 contains the digital interface receiver (or DIR) channel status and user data buffers. These
buffers correspond to the data contained in the C and U bits of the previously received block of the
AES3-encoded data stream. The contents of these buffers may be read through the SPI or I
2
C serial host
interface and processed as needed by the host system. See Table 5 for the DIR channel status buffer map, and
Table 6 for the DIR user data buffer map.
32
Submit Documentation Feedback