Datasheet

www.ti.com
ELECTRICAL CHARACTERISTICS: General, DIR, and DIT
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
All specifications are at T
A
= +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
DIX4192
PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL I/O CHARACTERISTICS
(All I/O pins except line receivers and line driver)
High-level input voltage, V
IH
0.7 × VIO VIO V
Low-level input voltage, V
IL
0 0.3 × VIO V
High-level input current, I
IH
0.5 10 µ A
Low-level input current, V
IL
0.5 10 µ A
High-level output voltage, V
OH
I
O
= –4mA 0.8 × VIO VIO V
Low-level output voltage, V
OL
I
O
= +4mA 0 0.2 × VIO V
Input capacitance, C
IN
3 pF
LINE RECEIVER INPUTS
(RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)
Voltage across a given
Differential input sensitivity, V
TH
150 200 mV
differential input pair
Input hysteresis, V
HY
150 mV
LINE DRIVER OUTPUTS
(TX+, TX–)
Differential output voltage, V
TXO
R
L
= 110 Ω Across TX+ and TX– 5.4 V
PP
MASTER CLOCK INPUT
Master clock input (MCLK) frequency, f
MCLK
1 27.7 MHz
Master clock input (MCLK) duty cycle, f
MCLKD
45 55 %
DIGITAL AUDIO INTERFACE RECEIVER (DIR)
PLL lock range 20 216 kHz
Reference clock input (RXCKI) frequency, f
RXCKI
3.5 27.7 MHz
Reference clock input (RXCKI) duty cycle, f
RXCKID
45 55 %
Recovered clock output (RXCKO) frequency, f
RXCKO
3.5 27.7 MHz
Recovered clock output (RXCKO) duty cycle, f
RXCKOD
45 55 %
Recovered clock output (RXCKO) intrinsic jitter Measured cycle-to-cycle 250 ps RMS
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
Intrinsic output jitter Measured cycle-to-cycle 200 ps RMS
3
Submit Documentation Feedback