Datasheet

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APPLICATIONS INFORMATION
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
Typical application diagrams and power-supply connections are presented in this section to aid the customer in
hardware designs employing the DIX4192 device.
Figure 22 illustrates typical application connections for the DIX4192 using an SPI host interface. The SPI host
will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to
providing the SPI bus master, the host may be utilized to process interrupt and flag outputs from the DIX4192.
The audio serial ports are connected to external digital audio devices, which may include data converters, digital
signal processors, digital audio interface receivers/transmitters, or other logic devices. The DIR inputs and DIT
outputs are connected to line, optical, or logic interfaces (see the Receiver Input Interfacing and Transmitter
Output Interfacing sections). Master and DIR reference clock sources are also shown.
Figure 23 illustrates typical application connections for the DIX4192 using an I
2
C bus interface. The I
2
C bus
master will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to
providing the I
2
C bus master, the host may be used to process interrupt and flag outputs from the DIX4192.
Pull-up resistors are connected from SCL (pin 20) and SDA (pin 22) to the VIO supply rail. These resistors are
required for the open drain outputs of the I
2
C interface. All other connections to the DIX4192 are the same as
the SPI host case discussed previously.
Figure 24 illustrates the recommended power-supply connections and bypassing for the DIX4192. In this case, it
is assumed that the VIO, VDD33, and VCC supplies are powered from the same +3.3V power source. The
VDD18 core supply is powered from a separate supply, or derived from the +3.3V supply using a linear voltage
regulator, as illustrated with the optional regulator circuitry of Figure 24 .
The 0.1 µ F bypass capacitors are surface-mount X7R ceramic, and should be located as close to the device as
possible. These capacitors should be connected directly between the supply and corresponding ground pins of
the DIX4192. The ground pin is then connected directly to the ground plane of the printed circuit board (PCB).
The larger value capacitors, shown connected in parallel to the 0.1 µ F capacitors, are recommended. At a
minimum, there should at least be footprints on the PCB for installation of these larger capacitors, so that
experiments can be run with and without the capacitors installed, in order to determine the effect on the
measured performance of the DIX4192. The larger value capacitors can be surface-mount X7R multilayer
ceramic or tantalum chip.
The substrate ground, BGND (pin 44), should be connected by a PCB trace to AGND (pin 10). The AGND pin is
then connected directly to the ground plane. This connection helps to reduce noise in the DIR section of the
device, aiding the overall jitter and noise tolerance for the receiver.
A series resistor is shown between the +3.3V supply and VCC (pin 9) connection. This resistor combines with
the bypass capacitors to create a simple RC filter to remove higher frequency components from the VCC supply.
The series resistor should be a metal film type for best filtering characteristics. As a substitute for the resistor, a
ferrite bead can be utilized, although it may have to be physically large in order to contribute to the filtering.
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