Datasheet

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S A A A A A P
Byte1
Slav Ade dress
wit Rh /W=0
Byte2
Reg tis erAddressByte
wit Ih NC=1
Byte3
SlaveAddress
withR/W=1
Byte4
Reg tis erData
ByteN
Reg tis erData
forAddress+N
(c)RandomReadOp mentEnablederation,Auto-Incre
S=STARTC dion tion
A=Ackn w dgo le e
A =NotAckno ledgew
R=Repeated TARTS
P=STOPCondii nt o
Transferfrom steMa r to Slave
Transferfrom avetoSl Master
L gende
R
S A A P
Byte1
SlaveAddre ss
withR/W=1
Byte2
Reg tis erAddressByte
withINC=0
(a Cu) rrentAd res heRegister ddr ss fthe vio sd A e Pre us Read,Assumest o
S A A
A P
Byte1
Slav Ade dress
withR/W=0
Byte2
Reg tis erAddressByte
withINC=0
Byte3
Slav Ade dress
withR/W=1
(b)RandomReadOp me tDisablederation,Auto-Incre n
R
A
Byte4
RegisterData
INTERRUPT OUTPUT
VIO
10kW
Tothe outputsfINT or
additionalDIX4192 devices
Interrupt
Logic
DIX4192 MCU,DSP,
orLogic
INT
23
Interrupt
Input
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
Figure 20. Fast/Standard Mode Read Operations
The DIX4192 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The
interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pull-up
resistor to the VIO supply rail. The value of the pull-up is not critical, but a 10k Ω device should be sufficient for
most applications. Figure 21 shows the interrupt output pin connection. The open-drain output allows interrupt
pins from multiple DIX4192 devices to be connected in a wired OR configuration.
Figure 21. Interrupt Output Pin Connections
24
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