Datasheet

www.ti.com
A6 A5 A4 A3 A2 A1 A0
1 1 1 0 0 A1 A0 R/W
Se yt b Pin 91
Se yt b Pin 12
MSB
LSB
Fir ts Byte After o itthe RSTA T/RESTART C ond i n
Slave Address
A6 A5 A4 A3 A2 A1 A0INC
MSB LSB
(a)DIX419 lave2 S Address
(b)Regist rAddree ssByte
Auto-In ecrem nt
0=Disabled
1=Enabled
S A A A P
S A A A A A P
Byte1
SlaveAddress
withR/W=0
Byte2
RegisterAddressByte
withINC=0
Byte3
Reg sti er
Daat
Byte1
SlaveAddress
withR/W=0
Byte2
RegisterAddressByte
withINC=1
Byte3
RegisterData
Byte4
RegisterData
fo Addr ress+1
ByteN
Register Data
forAddress+N
(a)WritingaSingleRegister
(b) rW iting ult istersUsing uto-Incr m ntOperationM ip A eleSe uentialR gq e e
S=STAR oT n iCo d ti n
A=Acknowl d ee g
P=STOPCondii nt o
Transferfrom steMa r to Slave
TransferfromSlaveto Master
Legend
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
Figure 20 illustrates the protocol for Standard and Fast mode Read operations. The current address read
operation of Figure 20 (a) assumes the value of the register address from the previously executed write or read
operation, and is useful for polling a register address for status changes. Figure 20 (b) and Figure 20 (c) illustrate
read operations for one or more random register addresses, with or without auto-increment mode enabled.
Figure 18. DIX4192 Slave Address and Register Address Byte Definitions
Figure 19. Fast/Standard Mode Write Operations
23
Submit Documentation Feedback