Datasheet

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CS
CDNI
CC KL
Set =1hereto gisterlocation.write/readonereCS
Hold =0toenab de.leauto-incrementmoCS
Byte0 Byte1 Byte2 Byte3
ByteN
R/W A6 A5 A0A4 A1A3 A2
Setto 0forWrite ad.; Setto orRe1f
Byte0:
MSB LSB
ByteDefi itionn
Header
RegisterData
RegisterAddress
Byte1:DontCar’ e
Byte2 throughByteN: RegisterD ta a
CDOUT
HiZ HiZ DataforA[ : ]+16 0DataforA[6:0]
DataforA[ : ]+N2 0
RegisterData
HOST INTERFACE OPERATION: PHILIPS I
2
C MODE
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
The SPI port supports write and read operations for multiple sequential register addresses through the
implementation of an auto-increment mode. As shown in Figure 17 , the auto-increment mode is invoked by
simply holding the CS input low for multiple data bytes. The register address is automatically incremented after
each data byte transferred, starting with the address specified by the command byte.
Refer to the Electrical Characteristics: SPI Interface table and Figure 2 for specifications and a timing diagram
that highlight the key parameters for SPI interface operation.
Figure 17. Serial Peripheral Interface (SPI) Protocol for the DIX4192
The DIX4192 supports a 2-wire Philips I
2
C bus interface when CPM (pin 18) is forced high or pulled up to the
VIO supply rail. The DIX4192 functions as a Slave-only device on the bus. Standard and Fast modes of
operation are supported. Standard mode supports data rates up to 100kbps, while Fast mode supports data
rates up to 400kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes
referred to as Fast/Standard, or F/S mode. The I
2
C Bus Specification (Version 2.1, January 2000), available
from Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the
reader is familiar with this specification. Refer to the Electrical Characteristics: I
2
C Standard and Fast Modes
table and Figure 3 for specifications and a timing diagram that highlight the key parameters for I
2
C interface
operation.
When the I
2
C mode is invoked, pin 20 becomes SCL (which serves as the bus clock) and pin 22 becomes SDA
(which carries the bi-directional serial data for the bus). Pins 19 and 21 become A0 and A1, respectively, and
function as the hardware configurable portion of the 7-bit slave address.
The DIX4192 utilizes a 7-bit Slave address; see Figure 18 (a). Bits A2 through A6 are fixed and bits A0 and A1
are hardware programmable using pins 19 and 21, respectively. The programmable bits allow for up to four
DIX4192 devices to be connected to the same bus. The slave address is followed by the Register Address Byte,
which points to a specific register or data buffer location in the DIX4192 register map. The register address byte
is comprised of seven bits for the address, and one bit for enabling or disabling auto-increment operation; see
Figure 18 (b). Auto-increment mode allows multiple sequential register locations to be written to or read back in a
single operation, and is especially useful for block write and read operations.
Figure 19 illustrates the protocol for Standard and Fast mode Write operations. When writing a single register
address, or multiple non-sequential register addresses, the single register write operation of Figure 19 (a) may be
used one or more times. When writing multiple sequential register addresses, the auto-increment mode of
Figure 19 (b) improves efficiency. The register address is automatically incremented by one for each successive
byte of data transferred.
22
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