Datasheet

www.ti.com
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
10
0
10
1
10
2
10
3
JitterFrequency(Hz)
10
4
10
5
10
6
JitterAttenuation(dB)
PeakJitter(UI)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20 100 1k
SinusoidalJitterFrequency(Hz)
10k 100k
THD+NRatio(dB)
5
2
1
500m
200m
100m
50m
20m
10m
5m
2m
1m
THD+N
OutputJitterAmplitude
InputJitterAmplitude
Ch2.Ch. 1 Ch. 1Ch2. Ch2.Ch. 1 Ch. 1Ch2.
BLS
(output)
SY CN
(output)
CorU daat
(output)
Bit 0 Bit 1 Bit 2 Bit 4 ¼
Block Start
(Fr mea 0St rtsHea re)
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
PRODUCT OVERVIEW (continued)
The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock
output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status
flags may be output at the general-purpose output (GPO) pins, or accessed through the status registers via the
SPI or I
2
C host interface. Refer to the General-Purpose Digital Outputs and Control Registers sections for
additional information regarding the DIR status functions.
Figure 14. DIR Jitter Attenuation Characteristics
Figure 15. DIR Jitter Tolerance Plot
Figure 16. DIR Channel Status and User Data Serial Output Format Via the GPO Pins
20
Submit Documentation Feedback