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SY CN
BLS
(input)
BLS
(output)
Block Start
(Frame 0startshere)
DIGITAL INTERFACE RECEIVER (DIR) OPERATION
PL 1L
AE 3S
Decoder
Pulse
Generator
PL 2L
128f
S
256f
S
512f
S
Clock
Divider
Divide by
1,2, 4,or8
DataStream
De-M xu
RX1+(pin1)
RX1 (pin2)-
RX2+(pin3)
RX2 (pin4)-
RX3+(pin5)
RX3 (pin6)-
RX4+(pin7)
RX4 (pin8)-
LOCK
(pin 11)
RXCKO
(pin 12)
RXCKO
BYPMUX[10: ]
R MUX[X 1:0]
RXCLK
MC KL
RXCKI
RXCKOF[1:0]
Ch1.
(Left)
Audio
Ch2.
(Right)
Audio
Cha nen l
Status
Channel
Status
User
Daat
User
Daat
UserAccess
(UA)Buffers
Receiver
Access
(RA)Buffers
To
DIT
ToSPI orI CHostInterface
2
Receiver
Sy cn
Generator
RCV_SYNC
Errorand
StatusOutputs
ToDIT Buffer
andLine Driver
Reference
Clock
Source
To
DIT
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
PRODUCT OVERVIEW (continued)
Figure 11. DIT Block Start Timing
The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The
lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 12 shows the functional
block diagram for the DIR.
Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers
can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with
CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 13 for a simplified
schematic for the line receiver. External connections are discussed in the Receiver Input Interfacing section.
Figure 12. Digital Interface Receiver (DIR) Functional Block Diagram
18
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