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RESET OPERATION
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
PRODUCT OVERVIEW (continued)
Figure 4 shows a simplified functional block diagram for the DIX4192. Additional details for each function block
will be covered in respective sections of this datasheet.
Figure 4. Functional Block Diagram
The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the
internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset
low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation
using either the SPI or I
2
C port for at least 500 µ s after the rising edge of RST. See Figure 5 for the reset timing
sequence of the DIX4192.
In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby
all registers and buffers are forced to their default settings. Refer to the Control Registers section for details
regarding the RESET bit function.
Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception
of the SPI or I
2
C host interface and the corresponding control registers. The user may then program the
DIX4192 to the desired configuration, and release the desired function blocks from the power-down state
utilizing the corresponding bits in control register 0x01.
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