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SCKO (O)
BCKO (O)
LRCKO (O)
XTI (I)
XTO (O)
VCO
RXIN
Built-in PLL
Clock Recovery
1/N
1/N
PLL Clock Source
1/N
1/4
1/64
XTI Clock Source
CKSEL (I)
Oscillation Amplifier
ClockSource
Selector
[PSCK1]
[PSCK0]
PLL Clock Source (Built-In PLL and VCO) Description
DIR9001
SLES198 – DECEMBER 2006
Figure 7. Clock Tree Diagram
The DIR9001 has on-chip PLL (including VCO) for recovering the clock from the biphase input signal.
The clock that is output from the built-in VCO is defined as the PLL clock source.
In the locked state, the built-in PLL generates a system clock that synchronizes with the biphase input signal.
In the unlocked state, the built-in PLL (VCO) generates a free-running clock. (The frequency is not constant.)
The PLL can support a system clock of 128 f
S
, 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the sampling frequency of
the biphase input signal.
The system clock frequency of the PLL is selected by PSCK[1:0].
The DIR9001 can decode a biphase input signal through its 28 sampling-frequency range of kHz to 108 kHz,
independent of the setting of PSCK[1:0].
Therefore, the DIR9001 can decode a biphase input signal with a sampling frequency from 28 kHz to 108 kHz at
all settings of PSCK[1:0]
The relationship between the PSCK[1:0] selection and the output clock (SCKO, BCKO, LRCKO) from the PLL
source is shown in Table 3 .
Table 3. SCKO, BCKO, and LRCKO Frequencies Set by PSCK[1:0]
PSCK[1:0] SETTING OUTPUT CLOCK FROM PLL SOURCE
PSCK1 PSCK0 SCKO BCKO LRCKO
L L 128 f
S
64 f
S
f
S
L H 256 f
S
64 f
S
f
S
H L 384 f
S
64 f
S
f
S
H H 512 f
S
64 f
S
f
S
14
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