Network Router User Manual

Lead 1
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XA[0:18]
XD[0:15]
XREADY(Synch)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
WS (Synch)
XZCS0AND1
, XZCS2,
XZCS6AND7
XRD
XWE
XR/W
t
d(XCOH-XZCSL)
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access
to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n − 1) t
c(XTIM)
− t
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) t
c(XTIM)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
h(XD)XWEH
t
su(XRDHsynchH)XCOHL
t
su(XRDYsynchL)XCOHL
DOUT
t
d(XWEL-XD
)
t
dis(XD)XRNW
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
= Don’t care. Signal can be high or low during this time.
Legend:
See Note E
See Note D
See
Notes A
and B
See Note C
t
e(XRDYsynchH)
SM320F2812-HT
www.ti.com SGUS062A–JUNE 2009–REVISED APRIL 2010
Figure 6-33. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE
0 = XREADY
N/A
(1)
N/A
(1)
N/A
(1)
1 0 ≥ 1 3 ≥ 1
(Synch)
(1) N/A = "Don't care" for this example
Copyright © 2009–2010, Texas Instruments Incorporated Electrical Specifications 129
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