Datasheet

DF1704
6
SBAS099A
RESET
The DF1704 has both an internal power-on reset circuit and
a reset pin, RST (pin 14), for providing an external reset
signal. The internal power-on reset is performed automati-
cally when power is applied to the DF1704, as shown in
Figure 2. The RST pin can be used to synchronize the
DF1704 with a system reset signal, as shown in Figure 3.
SYSTEM CLOCK REQUIREMENTS
The system clock of the DF1704 can be supplied by either
an external clock signal at XTI (pin 6), or by the on-chip
crystal oscillator. The system clock rate must run at 256f
S
,
384f
S
, 512f
S
, or 768f
S
, where f
S
is the audio sampling rate.
It should be noted that a 768f
S
system clock cannot be used
when f
S
= 96kHz. In addition, the on-chip crystal oscillator
is limited to a maximum frequency of 24.576MHz. Table I
shows the typical system clock frequencies for selected
sample rates.
The DF1704 includes a system clock detection circuit that
determines the system clock rate in use. The circuit com-
pares the system clock input (XTI) frequency with the
LRCIN input rate to determine the system clock multiplier.
Ideally, LRCIN and BCKIN should be derived from the
system clock to ensure proper synchronization. If the phase
difference between the system clock and LRCIN is larger
than ±6 bit clock (BCKIN) periods, the synchronization of
the system and LRCIN clocks will be performed automati-
cally by the DF1704.
Timing requirements for the system clock input are shown in
Figure 1.
AUDIO INPUT INTERFACE
The audio input interface is comprised of BCKIN (pin 2),
LRCIN (pin 28), and DIN (pin 1).
BCKIN is the input bit clock, which is used to clock data
applied at DIN into the DF1704’s input serial interface.
Input data at DIN is clocked into the DF1704 on the rising
edge of BCKIN. The left/right clock, LRCIN, is used as a
word latch for the audio input data.
BCKIN can run at 32f
S
, 48f
S
, or 64f
S
, where f
S
is the audio
sample frequency. LRCIN is run at the f
S
rate. Figures 4 (a)
through 4 (c) show the input data formats, which are sel-
ected by hardware or software controls. Figure 5 shows the
audio input interface timing requirements.
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY (f
S
) 256f
S
384f
S
512f
S
768f
S
32kHz 8.1920 12.2880 16.3840 24.5760
44.1kHz 11.2896 16.9340 22.5792 33.8688
(1)
48kHz 12.2880 18.4320 24.5760 36.8640
(1)
96kHz 24.5760
(3)
36.8640
(1)
49.1520
(1)
See Notes 1, 2
NOTES: (1) Maximum crystal oscillator frequency is 24.576MHz and cannot be used for these combinations. (2) 768f
S
system clock cannot be used with 96kHz
sampling rate. (3) Use external system clock applied at XTI.
TABLE I. Typical System Clock Frequencies.
FIGURE 1. System Clock Timing.
1024 system clocks
Reset
Reset Removal
V
DD
2.2V
2.6V
1.8V
Internal Reset
System Clock
FIGURE 2. Internal Power-On Reset Timing.
FIGURE 3. External Forces Reset Timing.
t
SCKH
System Clock Pulse Width HIGH :t
SCKIH
:7ns min
(1)
System Clock Pulse Width LOW :t
SCKIL
:7ns min
(1)
t
SCKL
2.0V
0.8V
“H”
“L”
XTI
NOTE: (1) For f
S
= 96kHz and SCK = 256f
S
, t
SCKIH
= 14ns (min)
t
SCKIL
= 14ns (min)
For f
S
≠ 96kHz and SCK = 256f
S
, t
SCKIH
= 20ns (min)
t
SCKIL
= 20ns (min)
1024 system (XTI) clocks
Reset
Reset Removal
System Clock
Internal Reset
RST
t
RST
t
RST
≥ 20ns
During the power-on reset period (1024 system clocks), the
DF1704 outputs are forced LOW. For an external forced
reset, the outputs are forced LOW during the initialization
period (1024 system clocks), which occurs after the LOW-
to-HIGH transition of the RST pin as shown in Figure 3.