Datasheet

DF1704
11
SBAS099A
FIGURE 10. Software Interface Timing Requirements.
1.4V
1.4V
1.4V
ML
(1)
MC
(2)
MD
NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. (3) SYSCK: System Clock Cycle.
t
MLH
t
MHH
t
MCH
t
MCL
t
MDS
t
MCY
t
MLS
t
MLL
t
MDH
LSB
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Hold Time
MD Set-Up Time
ML Low Level Time
ML High Level Time
ML Hold Time
(2)
ML Set-Up Time
(3)
t
MCY
t
MCL
t
MCH
t
MDH
t
MDS
t
MLL
t
MHH
t
MLH
t
MLS
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns + 1SYSCLK
(3)
(min)
40ns + 1SYSCLK
(3)
(min)
40ns (min)
40ns (min)
MODE0 Register
The MODE0 register is used to set the attenuation data for
the Left output channel, or DOL (pin 24).
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] is used for both the Left
and Right channel attenuators.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
AL[7:0] Left Channel Attenuator Data, where AL7 is the
MSB and AL0 is the LSB.
Attenuation Level is given by:
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFh, ATTEN = –0dB
For DATA = FEh, ATTEN = –0.5dB
For DATA = 01h, ATTEN = –127.5dB
For DATA = 00h, ATTEN = infinity = Mute
LDL Left Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenua-
tion levels of both the Left and Right channels.
When LDL = 1, the Left channel output level is
set by the data in AL[7:0]. The Right channel
output level is set by the data in AL[7:0], or the
most recently programmed data in bits AR[7:0]
of register MODE1.
When LDL = 0, the Left channel output data
remains at its previously programmed level.
MODE1 Register
The MODE1 register is used to set the attenuation data for
the Right output channel, or DOR (pin 23).
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] of register MODE0 is used
for both the Left and Right channel attenuators.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
AR[7:0] Right Channel Attenuator Data, where AR7 is
the MSB and AR0 is the LSB. Attenuation
Level is given by:
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFh, ATTEN = –0dB
For DATA = FEh, ATTEN = –0.5dB
For DATA = 01h, ATTEN = –127.5dB
For DATA = 00h, ATTEN = infinity = Mute
LDR Right Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenuation
levels of both the Left and Right channels.
When LDR = 1, the Right channel output level
is set by the data in AR[7:0], or by the data in
bits AL[7:0] of register MODE0. The Left chan-
nel output level is set to the most recently
programmed data in bits AL[7:0] of register
MODE0.
When LDR = 0, the Right channel output data
remains at its previously programmed level.