Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Custom audio Consumer audio, Professional audio I²S SSOP 28

Stereo, 24-Bit, 96kHz

8X Oversampling Digital Interpolation Filter

49%

FPO

DF1704

DESCRIPTION

The DF1704 is a high-performance, stereo, 8X oversampling

digital interpolation filter designed for high-end consumer

and professional audio applications. The DF1704 supports

24-bit, 96kHz operation and features user-programmable

functions, including selectable filter response, de-emphasis,

attenuation, and input/output data formats.

The DF1704 is the ideal companion for Texas Instruments’

PCM1704 24-bit audio digital-to-analog converter. This

combination allows for construction of very high-perfor-

mance audio systems and components.

FEATURES

● COMPANION DIGITAL FILTER FOR THE PCM1704

24-BIT AUDIO DAC

● HIGH PERFORMANCE FILTER:

Stopband Attenuation: –115dB

Passband Ripple:

0.00005dB

● AUDIO INTERFACE:

Input Data Formats: Standard, Left-

Justified, and I

Input Word Length: 16, 20, or 24 Bits

Output Word Length: 16, 18, 20, or 24 Bits

Sampling Frequency: 32kHz to 96kHz

● PROGRAMMABLE FUNCTIONS:

Hardware or Software Control Modes

Sharp or Slow Roll-Off Filter Response

Soft Mute

Digital De-Emphasis

Independent Left/Right Digital Attenuation

Serial

Input

I/F

Mode

Control

I/F

8X Oversampling

Digital Filter with

Function

Controller

Crystal/OSC

XTI

SCK

XTO CLKO(SF0) (SF1) (SRO) V

Output I/F

BCKO

(IW1)

(IW0)

(OW1)

(OW0)

WCKO

DOL

DOR

MC/LRIP

MD/CKO

LRCIN

DIN

BCKIN

MODE

ML/RESV

(MUTE)

RST

(DEM)

Power Supply

SBAS099A – MARCH 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

● SYSTEM CLOCK: 256f

, 384f

, 512f

, 768f

● ON-CHIP CRYSTAL OSCILLATOR

● +5V SINGLE-SUPPLY OPERATION

● SMALL SSOP-28 PACKAGE

Summary of content (20 pages)

PAGE 1
DF1704 D F1 704 49% FPO SBAS099A – MARCH 2001 Stereo, 24-Bit, 96kHz 8X Oversampling Digital Interpolation Filter TM ● ● ● ● FEATURES DESCRIPTION The DF1704 is a high-performance, stereo, 8X oversampling digital interpolation filter designed for high-end consumer and professional audio applications. The DF1704 supports 24-bit, 96kHz operation and features user-programmable functions, including selectable filter response, de-emphasis, attenuation, and input/output data formats.
PAGE 2
PACKAGE/ORDERING INFORMATION PRODUCT DF1704E PACKAGE PACKAGE DRAWING NUMBER SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA SSOP-28 324 –25°C to +85°C DF1704E DF1704E Rails ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage (VDD , VCC1, VCC2R, VCC2L) .................................... +6.5V Supply Voltage Differences ................................................................. ±0.1 GND Voltage Differences ............................
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ELECTRICAL CHARACTERISTICS All specifications at +25°C, VDD = +5V, unless otherwise noted.
PAGE 4
TYPICAL CHARACTERISTICS OF INTERNAL FILTER DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz) PASSBAND RIPPLE (Sharp Roll Off) 0.0001 0 0.00008 –20 0.00006 –40 Attenuation (dB) Attenuation (dB) FREQUENCY RESPONSE (Sharp Roll Off) 20 –60 –80 –100 –120 –140 0.00004 0.00002 0 –0.00002 –0.00004 –160 –0.00006 –180 –0.00008 –0.0001 –200 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 0.1 0.15 0.2 Frequency (fS) 0.25 0.3 0.35 0.4 0.45 0.
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TYPICAL CHARACTERISTICS OF INTERNAL FILTER (Cont.) DE-EMPHASIS (fS = 44.1kHz) 0 DE-EMPHASIS ERROR (fS = 44.1kHz) 0.01 0.008 –2 0.006 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.01 –10 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 Frequency (fS) DE-EMPHASIS (fS = 48kHz) 0 10 12 14 16 18 20 Frequency (fS) DE-EMPHASIS ERROR (fS = 48kHz) 0.01 0.008 0.006 –2 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.
PAGE 6
SYSTEM CLOCK REQUIREMENTS The system clock of the DF1704 can be supplied by either an external clock signal at XTI (pin 6), or by the on-chip crystal oscillator. The system clock rate must run at 256fS, 384fS, 512fS, or 768fS, where fS is the audio sampling rate. During the power-on reset period (1024 system clocks), the DF1704 outputs are forced LOW.
PAGE 7
(a) Standard Format (Sony Format); Lch = “H”, Rch = “L” 1/fS Lch Rch LRCIN BCKIN AUDIO DATA WORD = 16-BIT DIN 14 15 16 1 MSB AUDIO DATA WORD = 20-BIT DIN 18 19 20 1 MSB 22 23 24 1 1 15 16 2 LSB 2 AUDIO DATA WORD = 24-BIT DIN 15 16 2 19 20 1 2 19 20 23 24 1 2 23 24 LSB 2 MSB LSB MSB LSB (b) Left-Justified Format; Lch = “H”, Rch = “L” 1/fS Lch Rch LRCIN BCKIN AUDIO DATA WORD = 24-BIT DIN 1 2 22 3 MSB 23 24 1 2 22 3 MSB LSB 23 24 1 2 3 1 2 1 2 LSB (c) I2S Da
PAGE 8
AUDIO OUTPUT INTERFACE The audio output interface includes BCKO (pin 26), WCKO (pin 25), DOL (pin 24), and DOR (pin 23). The output data format used by the DF1704 for DOL and DOR is Binary Two’s Complement, MSB-first, right-justified audio data. Figures 6(a) and 6(b) show the output data formats for the DF1704. Figure 7 shows the audio output timing. BCKO is the output bit clock and is used to clock data into an audio Digital-to-Analog Converter (DAC), such as the PCM1704.
PAGE 9
tWCKP WCKO 0.5VDD tBCKH tBCKL tCKWK 0.5VDD BCKO tBCKP tCKDO DOL, R 0.
PAGE 10
PIN NAME PIN NUMBER DESCRIPTION REGISTER NAME BIT NAME DESCRIPTION MODE0 AL[7:0] LDL A[1:0] res Attenuation Data for the Left Channel Attenuation Load Control for the Left Channel Register Address Reserved MODE1 AR[7:0] LDL A[1:0] res Attenuation Data for the Right Channel Attenuation Load Control for the Right Channel Register Address Reserved MODE2 MUT DEM IW[1:0] OW[1:0] A[1:0] res Soft Mute Control Digital De-Emphasis Control Input Data Format and Word Length Output Data Word Length Regist
PAGE 11
tMLL tMHH ML(1) 1.4V tMCH tMLH tMCL tMLS 1.4V MC(2) tMCY LSB MD tMDS 1.4V tMDH MC Pulse Cycle Time tMCY 100ns (min) MC Pulse Width LOW tMCL 40ns (min) MC Pulse Width HIGH tMCH 40ns (min) MD Hold Time tMDH 40ns (min) MD Set-Up Time tMDS 40ns (min) ML Low Level Time tMLL 40ns + 1SYSCLK(3) (min) ML High Level Time tMHH 40ns + 1SYSCLK(3) (min) ML Hold Time(2) tMLH 40ns (min) ML Set-Up Time(3) tMLS 40ns (min) NOTES: (1) ML rising edge to the next MC rising edge.
PAGE 12
MODE2 Register The MODE2 register is used to program various functions: MODE3 Register The MODE3 register is used to program various functions. MUT I2 S Soft Mute Function. When MUT = 0, Soft Mute is ON for both Left and Right channels. When MUT = 1, Soft Mute is OFF for both Left and Right channels. DEM Digital De-Emphasis Function. When I2S = 0, standard or left-justified formats are enabled. When I2S = 1, the I2S formats are enabled.
PAGE 13
APPLICATIONS INFORMATION PCB LAYOUT GUIDELINES In order to obtain the specified performance from the DF1704 and its associated DACs, proper printed circuit board layout is essential. Figure 11 shows two approaches for obtaining the best audio performance. Figure 11(a) shows a standard, mixed signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The ground areas should be put on a split-plane, separate from the routing and power layers.
PAGE 14
(a) Layout Without Isolation Digital Power Supplies Common Ground Connection Analog Power Supplies WCKO BCKO DAC DOL DOR DF1704 DAC Digital Section Analog Section Split Ground Plane (b) Layout With Isolation Digital Power Supplies Analog Power Supplies WCKO BCKO ISO150 DAC DOL DOR DF1704 ISO150 Digital Section DAC Analog Section = DGND Split Ground Plane = AGND FIGURE 11. PCB Layout Model.
PAGE 15
DF1704 1 DIN 2 BCKIN 3 I2S BCKO 26 4 IW0 WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS NC 21 9 CLKO OW1 20 10 MODE OW0 19 Audio Data and Clock Source 22pF XTAL LRCIN 28 SRO 27 22pF (optional) 11 MD/CKO SF1 18 12 MC/LRIP SF0 17 13 ML/RESV DEM 16 14 RST Digital Logic or Manual Controls D/A Converters or Digital Couplers + C1 0.1µF C2 10µF +5V MUTE 15 7 7 = DGND NOTE: Do not allow pins 3-5, 11-20, and 27 to float.
PAGE 16
DIGITAL SECTION WORD CLOCK ANALOG SECTION DF1704 Digital Audio Input Digital Audio Receiver DATA 1 +5V Micro Controller or Logic BCKIN SRO 27 WCLK 3 I2 S BCKO 26 DATA 4 IWO WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS 9 CLKO OW1 20 10 MODE OW0 19 11 MD SF1 18 12 MC SF0 17 13 ML Post Filter Left Channel Out I/V Post Filter Right Channel Out PCM1704 DATA D/A Converter DEM 16 MUTE 15 10µF = DGND I/V BCLK WCLK System Reset D/A Converter NC 21 14 RST
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device DF1704E/2K Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 10.8 2.4 12.0 16.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DF1704E/2K SSOP DB 28 2000 336.6 336.6 28.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.