Datasheet

2 Circuit
+V
S
-V
S
C
1
C
2
R
11
+
+
C
3
C
5
L
1
P1
L
2
C
4
R
10
SD
SD
EN
ENABLE
A1
A1
GND
-V
S
V+
V-
A0
Logic
R
14
R
12
R
15
R
13
OUT
A0
+V
S
R
8
R
4
+IND
+INB
R
6
R
2
+INC
+INA
IN0
IN2
IN1
IN3
FB
OUT
R
9
3 Components
Circuit www.ti.com
The circuit schematic in Figure 2 shows the connections for all possible components. Each configuration
uses only some of the components.
Figure 2. Schematic for DEM-OPA-SO-1E
Components that have RF performance similar to the ones in Table 1 may be substituted.
Table 1. Component Descriptions
PART DESCRIPTION
C
5
, C
6
Tantalum Chip Capacitor, SMD EIA Size 3216, 20V
C
1
, C
3
, C
4
Multilayer Ceramic Chip Capacitor, SMD 0603, 50V
+INA, +INB, +INC, +IND, SD, ENABLE, A0, A1 SMA or SMB Board Jack (Amphenol 901-144-8)
L
1
, L
2
EMI-Suppression Ferrite Chip, SMD 0603 (Steward LI 0603 B 900 R)
P
1
Terminal Block, 3.5mm Centers (On-Shore Technology ED555/3DS)
R
XX
Metal Film Chip Resistor, SMD 0603, 1/8W
Refer to Figure 3 for the location of the following components:
• R
2
, R
4
, R
6
, R
8
, and R
9
set the I/O input impedance.
• R
10
and R
11
set the gain.
• R
12
, R
13
, R
14
, and R
15
set the I/O input impedance for the control pins A0, A1, SD, and EN.
• C
1
through C
5
are power supply bypass capacitors.
2 DEM-OPA-SO-1E Demonstration Fixture SBOU045A – May 2007 – Revised April 2009
Submit Documentation Feedback