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User's Guide

SLAU234A–October 2007–Revised July 2010

DDC11xEVM-PDK User's Guide

Figure 1. DDC11xEVM-PDK Photo

The DDC11xEVM-PDK is an evaluation kit for evaluating the DDC112 (dual channel) and DDC114 (quad

channel) current input 20-bit analog-to-digital (A/D) converters. The kit consists of a motherboard

(DDCMB) for interfacing to a PC, one DDC112 device board (DDC112EVM), and one DDC114 device

board (DDC114EVM). Easy-to-use software for the Microsoft Windows

operating system is included that

allows performance evaluation of either device. Complete circuit descriptions, schematic diagrams, and

bills of material are included in this user's guide.

The following related documents are available through the Texas Instruments web site at www.ti.com.

EVM-Compatible Device Data Sheets

Device Literature Number Device Literature Number

DDC112U SBAS085 SN74LVC07 SCES337

DDC114 SBAS255 REG113 SBVS031

OPA350 SBOS099 TPS75233 SLVS242

SN74LVC2T45 SCES516 SN105125 SLVS418

SN74LVC4245A SCAS375 LM4040A41 SLOS456

REG104 SBVS025

Windows, Microsoft, Windows XP, Excel are registered trademarks of Microsoft Corporation.

Spartan is a trademark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

SLAU234A–October 2007–Revised July 2010 DDC11xEVM-PDK User's Guide

Summary of content (43 pages)

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User's Guide SLAU234A – October 2007 – Revised July 2010 DDC11xEVM-PDK User's Guide Figure 1. DDC11xEVM-PDK Photo The DDC11xEVM-PDK is an evaluation kit for evaluating the DDC112 (dual channel) and DDC114 (quad channel) current input 20-bit analog-to-digital (A/D) converters. The kit consists of a motherboard (DDCMB) for interfacing to a PC, one DDC112 device board (DDC112EVM), and one DDC114 device board (DDC114EVM).
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www.ti.com 1 2 3 4 5 6 7 8 Contents Introduction .................................................................................................................. 3 DDC112 ...................................................................................................................... 3 DDC112EVM Hardware Description ..................................................................................... 5 DDC114 ..........................................................................................
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Introduction www.ti.com List of Tables 1 2 3 4 5 6 7 8 1 ....................................................................... 4 Jumper Setting Definitions for JP1 for the Voltage Reference Source for the DDC112 ........................... 7 Range Selection of the DDC114 .......................................................................................... 9 Power Option Jumpers for DDC114 DUT Board .......................................................................
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DDC112 www.ti.com The DDC112 continuously integrates the input signal by incorporating one dual integrator (A and B) per input channel. The output of the dual integrators are multiplexed into the A/D converter. In operation, one side of each input integrates the input charge, while the other side is being converted by the delta-sigma A/D converter and then reset. Figure 3 illustrates this operation. Another unique feature of the DDC112 is the option of external integrating capacitors.
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DDC112EVM Hardware Description www.ti.com Assuming a 10MHz system clock (pin 10 of the DUT), the relationship between the integration time, input current, and input charge is summarized in Equation 1 through Equation 3. QIN TINT = IIN(max) (1) TINT = VREF IIN(max) CINT (2) CINT = QIN VREF - 0.
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DDC112EVM Hardware Description www.ti.com Proper grounding and shielding practices should be taken into consideration when designing the circuit layout for the DDC112. In the event that the application cannot tolerate the additional shields of the DDC112EVM DUT board, an alternative layout is shown in Figure 4, where a PC ground plane is placed around the inputs of the DDC112 (pins 1 and 28). This shield helps minimize coupled noise into the input pins.
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DDC112EVM Hardware Description www.ti.com Table 2. Jumper Setting Definitions for JP1 for the Voltage Reference Source for the DDC112 Jumper Setting 3.2 Jumper Setting Function Position A Connects the 4.096V onboard reference to the DUT. Position B Connects the EXT VREF connector, J5, to the DUT. Position C Connects the breadboard VREF bus to the DUT.
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DDC114 www.ti.com External capacitors can be inserted in the C10, C11, C12, and C13 positions, as shown in Figure 6. These external capacitors can be used to set the gain of the DDC112U (DUT) to user specifications instead of the seven internal gains available. Refer to the DDC112 portion of this user guide for more details concerning the appropriate value of these external capacitors. For further detailed information, also refer to the DDC112 product data sheet.
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DDC114EVM Hardware Description www.ti.com For each of the four inputs, the DDC114 provides a dual-switched integrator front-end. This design allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. Adjustable full-scale ranges from 12pC to 350pC and adjustable integration times from 50ms to 1s allow currents from fAs to mAs to be measured with outstanding precision. Low-level linearity is ±0.
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DDCMB Hardware Description www.ti.com The inputs to the DDC114 device can be provided individually on the J6–J9 (AIN1 to AIN4) BNC connectors. For testing purposes, all four channels can be driven with the same signal if it is provided on J5 (AINCOM). Each of the four input channels connect to a jumper (JP4–JP7) for selecting whether the input is common (AINCOM), or if each input is individually connected through the BNC connectors (J6–J9).
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DDC11xEVM-PDK Kit Operation www.ti.com 6.3 Motherboard Switches S1, RESET_USB, resets the USB controller. Pushing this switch may be necessary if the DDCMB is not recognized by your PC when connecting it to the DDCMB. S2, RESET_FPGA, resets the FPGA. Normally, it should not be necessary to use this switch. 6.4 Hardware LEDs on the Motherboard A number of LED indicators are on the DDCMB. These indicators allow ease of monitoring the state the motherboard is in.
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DDC11xEVM-PDK Kit Operation www.ti.com Figure 8. Initial Found New Hardware Wizard Screen Figure 9. Driver Selection for DDC USB Motherboard drv.
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DDC11xEVM-PDK Kit Operation www.ti.com Figure 10. Select to Search Removable Media to Find Drivers on CD NOTE: You may see notices (Figure 11) that the drivers are not digitally signed, and given the option to accept the drivers anyway. Choose Continue Anyway. Figure 11.
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DDC11xEVM-PDK Kit Operation www.ti.com Figure 12. Copying Driver Files Figure 13.
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DDC11xEVM-PDK Kit Operation www.ti.com After the first driver is installed, disconnect and reconnect the USB cable to the DDCMB, or press the RESET_USB button on the DDCMB. This step causes the second driver to be installed. You will then see screens similar to those in Figure 14 through Figure 16. Figure 14. Driver Selection for DDC USB Motherboard drv.2 Figure 15.
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DDC11xEVM-PDK Kit Operation www.ti.com Figure 16. Copying Files for Additional Driver Once the USB drivers are installed, the DDC11x Evaluation program can be installed. Double-click on setup.exe in the install directory. A screen similar to that shown in Figure 17 appears. Figure 17.
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DDC11xEVM-PDK Kit Operation www.ti.com Next, the screen shown in Figure 18 appears. Verify that the installation directory is correct, and press the large button in the upper left corner of this screen to proceed. Figure 18. Choose Software Installation Directory When the installer completes copying files, the screen shown in Figure 19 appears. Figure 19. Software Installation Complete The software installation is now complete. Disconnect power from the DDCMB and proceed to the next section. 7.
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DDC11xEVM-PDK Kit Operation www.ti.com From the Windows Start menu, select the DDC112_114_Evaluation program. The program starts and displays a window as shown in Figure 20. Figure 20.
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DDC11xEVM-PDK Kit Operation www.ti.com From the Daughtercard drop-down menu at the top of this screen (Figure 21), select the daughtercard that is attached to the DDCMB. The settings shown on the FPGA Control tab are populated with the appropriate settings for the device connected. Figure 21. Daughtercard Selection Next, do a system refresh of the FPGA by clicking on the Refresh All button, located in the upper right corner of this screen.
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DDC11xEVM-PDK Kit Operation 7.3.1 www.ti.com Main Window Controls A number of controls are always visible, regardless of the tab selected in the main tab control. The Quit button causes the program to exit and releases system resources. The Refresh All button updates the state of all FPGA registers and pins to those states set in the FPGA control tab.
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DDC11xEVM-PDK Kit Operation www.ti.com • • • • • • • FORMAT: Choose how many bits wide the output word is on the DOUT line (16- or 20-bit). This option does not correspond to the FORMAT pin on the DDC114. It only controls the FPGA, and should be left at 20 bits for the DDC112 for proper operation. Channel Count: Number of channels to read back. Only the 2 or 4 settings are valid for the DDC112 or DDC114.
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DDC11xEVM-PDK Kit Operation 7.3.4 www.ti.com Data Summary Tab This tab displays the data in summary form. It displays all the channels, the average value measured by the channels, the RMS noise of the measured data, the peak-to-peak noise of the measured data, and the units that all these measurements are reported in. It also displays the RMS noise of all channels averaged together at the very top left. Figure 22.
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DDC11xEVM-PDK Kit Operation www.ti.com 7.3.5 Graph Tab The graph tab displays a graph of data versus sample acquired. It always displays the readings in codes, regardless of the Formatting settings. The channel to display is selected using the Channel combo box on the bottom of the graph. Figure 23. Graph Tab Left-clicking and dragging a box zooms in to the selected section of the graph. Right-clicking on the graph brings up limited zoom, format, print, and display features.
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DDC11xEVM-PDK Kit Operation 7.4 www.ti.com Troubleshooting 1. If you see a dialog box as shown in Figure 24, or an error message seen on main window status bar saying Error Writing Registers, this message indicates that the DDCMB is either not connected via USB or has not been properly detected by the system. Verify that the USB connection is good, or press the RESET_USB (S1) button on the DDCMB to allow communication to be established. Figure 24.
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Schematics and Layout www.ti.com 8 Schematics and Layout Full-size schematics for the DDC112EVM, DDC114EVM, and DDCMB boards are appended to this user's guide. The bills of material for each board are provided in Section 8.1. Figure 25.
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Schematics and Layout www.ti.com Figure 26.
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Schematics and Layout www.ti.com Figure 27.
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Schematics and Layout www.ti.com Figure 28.
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Schematics and Layout www.ti.com Figure 29.
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Schematics and Layout www.ti.com Figure 30.
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Schematics and Layout www.ti.com Figure 31. Silkscreen of DDCMB Motherboard Figure 32.
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Schematics and Layout www.ti.com Figure 33. Mid Layer 1 of DDCMB Motherboard Figure 34.
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Schematics and Layout www.ti.com Figure 35. Bottom Layer of DDCMB Motherboard Figure 36.
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Schematics and Layout 8.1 www.ti.com Bills of Material NOTE: All components should be RoHS compliant. Some part numbers may be either leaded or RoHS. Verify that purchased components are RoHS compliant. Table 6. DDC112EVM Bill of Materials Item No. 34 Qty Value Ref Designator C10, C11, C12, C13 Description Part Number K271J15C0GF5TL2 1 4 270pF 2 7 0.1mF C2, C3, C4, C14, Ceramic chip capacitor, 0.
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Schematics and Layout www.ti.com Table 7. DDC114EVM Bill of Materials Item No. Qty Value Ref Designator Description Vendor Part Number Ceramic chip capacitor, 0.1mF 50V ±10%, X7R 0603 Murata GRM188R71H104KA93D Ceramic chip capacitor, 0.33mF 16V ±10%, X7R 0603 Murata GRM188R71C334KA01D 1 10 0.1mF C1, C2, C3, C4, C5, C6, C7, C8, C9, C10 2 1 0.
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Schematics and Layout www.ti.com Table 8. DDCMB Bill of Materials Item No. Qty Value Ref Designator Description 1 2 10pF C1, C2 50V Ceramic chip capacitor, ±5%, C0G, 0603 Murata GRM1885C1H100JA01D 2 3 47pF C36, C37, C38 50V Ceramic chip capacitor, ±5%, C0G, 0603 Murata GRM1885C1H470JA01D Murata GRM188R71H103MA01D 36 Vendor Part Number 3 3 0.01mF C32, C35, C40 50V Ceramic chip capacitor, ±10%, X7R, 0603 4 25 0.
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Revision History www.ti.com Table 8. DDCMB Bill of Materials (continued) Value Ref Designator Item No. Qty 45 1 N/A DDCMB PWB Description Texas Instruments Vendor 6490016 Part Number 46 4 N/A Machine screws, Phillips lead 6-32 x 5/16 Building Fasteners PMSSS 632 0031 PH 47 4 N/A Hex standoff 6-32, 0.5" Keystone Electronics 2210 48 3 N/A Shorting block Samtec SNT-100-BK-G-H Revision History Changes from Original (October, 2007) to A Revision ..................................
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1 2 3 4 5 6 REVISION HISTORY REV ENGINEERING CHANGE NUMBER APPROVED D D +5V +5V C17 +5V 0.1uF R3 4.99K +5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 C 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 8 7 6 5 +3.3V TEST VCCB B1 B2 DIR 1 2 3 4 VCCA A1 A2 GND +3.3V 0.1uF 0.1uF DVALID CONV DOUT 22 2 RANGE0 RANGE2 CLK +5V VCCB VCCB B1 B2 B3 B4 B5 B6 B7 B8 OE DIR 0.1uF 0.1uF VCCA A1 A2 A3 A4 A5 A6 A7 A8 GND GND GND 1 C5 0.
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1 2 3 4 5 6 REVISION HISTORY REV ANY SPECIFICATIONS, DRAWINGS OR REPRINTS, OR DATA FURNISHED TO BIDDER OR SELLER SHALL REMAIN TEXAS INSTRUMENTS TUCSON CORPORATIONS'S PROPERTY, SHALL BE KEPT CONFIDENTIAL SHALL BE USED ONLY FOR THE PURPOSE OF COMPLYING WITH TEXAS INSTRUMENTS TUCSON CORPORATION QUOTATION OR WITH TEXAS INSTRUMENTS TUCSON CORPORATION PURCHASER ORDERS, SHALL NOT BE DISCLOSED TO THIRD PARTIES, AND SHALL BE RETURNED AT TEXAS INSTRUMENTS TUCSON CORPORATIONS'S REQUEST.
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1 2 3 4 5 6 REVISION HISTORY REV ENGINEERING CHANGE NUMBER APPROVED USB and Support Circuitry U2 1 PD5 2 1 3 PD6 D1 3 2 PD7 LED 511 4 xDGND 5 PAN_EXCCET222U USB_CLKOUT 6 V3p3 7 xDGND 8 xDGND C1 SLRD 9 L1 xDGND SLWR 10 FERRITE BEAD 10pF V3p3 X1 11 24MHz 1 12 C2 2 13 xDGND xDGND 3 14 10pF V3p3 4 15 16 17 xDGND 18 V3p3 19 xDGND L2 20 IFCLK FERRITE BEAD 21 xDGND 22 xDGND 23 V3p3 24 V3p3 25 PB0 U1 26 PB1 24LC00 27 PB2 R2 R3 1 8 28 NC VCC PB3 2 7 2.21k 2.
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1 2 3 4 5 6 REVISION HISTORY REV PB2 PB3 V1p2 V3p3 xDGND 1 3 5 7 9 11 13 2 4 6 8 10 12 14 V3p3 A15 A16 A17 A18 JTAG RAM xDGND V3p3 FOR XC3S250E144, VCCO; U7 C11 0.1uF C12 0.1uF C13 0.1uF C14 0.1uF xDGND xDGND A19 WE I/O7 I/O6 I/O5 I/O4 xDGND V3p3 V2p5 A3 A4 I/O1 I/O0 A2 V2p5 FOR XC3S250E144, VCCAUX; U7 V1p2 C16 0.1uF C17 0.1uF C18 0.
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Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.