Datasheet

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SBAS325B − JUNE 2004 − REVISED APRIL 2009
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8
THEORY OF OPERATION
The block diagram of the DDC118 is shown in Figure 1.
The device contains eight identical input channels that
perform the function of current-to-voltage integration
followed by a multiplexed A/D conversion. Each input has
two integrators so that the current-to-voltage integration
can be continuous in time. The output of the sixteen
integrators are switched to four delta-sigma (∆Σ)
converters via four four-input multiplexers. With the
DDC118 in the continuous integration mode, the output of
the integrators from one side of the inputs will be digitized
while the other eight integrators are in the integration
mode, as illustrated in the timing diagram in Figure 2. This
integration and A/D conversion process is controlled by
the system clock, CLK. The results from side A and side
B of each signal input are stored in a serial output shift
register. The DVALID
output goes low when the shift
register contains valid data.
Dual
Switched
Integrator
Dual
Switched
Integrator
∆Σ
Modulator
Digital
Filter
Digital
Input/Output
FORMAT
DCLK
DCLK
DVALID
DOUT
DOUT
DIN
DIN
Control
IN3
IN1
VREF
DGND
DVDD
AGND
AVDD
Dual
Switched
Integrator
Dual
Switched
Integrator
∆Σ
Modulator
Digital
Filter
IN4
IN2
Dual
Switched
Integrator
Dual
Switched
Integrator
∆Σ
Modulator
Digital
Filter
IN7
IN5
Dual
Switched
Integrator
Dual
Switched
Integrator
∆Σ
Modulator
Digital
Filter
IN8
IN6
CLK
CONV
RANGE0
RANGE1
RANGE2
TEST
CLK_4X
HISPD/LOPWR
RESET
Figure 1. DDC118 Block Diagram