Datasheet

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SBAS325B − JUNE 2004 − REVISED APRIL 2009
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16
t
12
t
12
t
14
t
13
T
INT
T
INT
End Integration Side A
Start Integration Side B
Side A
Side A
Data Ready
Side B
Data Ready
Side A
Side A
End Integration Side B
Start Integration Side A
End Integration Side A
Start Integration Side B
CONV
DVALID
A/D Conversion
Inputs 1, 2, 5, and 6 (Internal)
A/D Conversion
Inputs 3, 4, 7, and 8 (Internal)
t
14
t
13
Side B
Side B
Figure 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC118
Table 7. Timing for the Internal Operation in Continuous Mode
CLK = 4MHz, CLK_4X = 0 CLK = 4.8MHz, CLK_4X = 0
SYMBOL DESCRIPTION
MIN TYP MAX MIN TYP MAX
UNITS
T
INT
Integration Period (continuous mode) 400 1,000,000 320 1,000,000 µs
t
12
A/D Conversion Time (internally controlled) 169.5 141.25 µs
t
13
A/D Conversion Reset Time (internally controlled) 4 3.333 µs
t
14
Integrator and A/D Conversion Reset Time
(internally controlled)
23 19.167 µs