Datasheet

DDC112
26
SBAS085B
www.ti.com
FIGURE 30. Recommended Shield for DDC112U Layout
Design.
FIGURE 29. Power Supply Connection Options.
DDC112
0.1µF
< 10
10µF
V
S
+
One +5V Supply
AV
DD
DV
DD
AV
DD
DV
DD
DDC112
0.1µF
0.1µF
0.1µF
10µF
V
S
+
Separate +5V Supplies
10µF
V
DD
+
Input shielding practices should be taken into consideration
when designing the circuit layout for the DDC112. The inputs
to the DDC112 are high impedance and extremely sensitive
to extraneous noise. Leakage currents between the PCB
traces can exceed the input bias current of the DDC112 if
shielding is not implemented. Figure 30 illustrates an accept-
able approach to this problem. A PC ground plane is placed
around the inputs of the DDC112. This shield helps minimize
coupled noise into the input pins. Additionally, the pins that
DDC112U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Digital I/O
and
Digital Power
Digital I/O
and
Digital Power
Shield
external
caps when
used
Analog
Ground
Analog
Power
Shield
external
caps when
used
Analog
Ground
Analog
Ground
IN1 IN2
Analog
Ground
are used for the external integration capacitors should be
guarded by a ground plane when the external capacitors are
used.
The approach above reduces leakage affects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather than
into the analog input stage of the DDC112.