Datasheet

DDC112
25
SBAS085B
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T
INT
T
INT
t
30
T
INT
T
INT
t
31
Side A
Data
Side B
Data
CONV
DVALID
DXMIT
DCLK
DOUT
FIGURE 27. Readback in Noncontinuous Mode.
FIGURE 28. Timing Diagram at Power-Up of the DDC112.
t
32
t
33
Integrate Side A
Integrate Side B
Power-Up
Initialization
Release State
Start
Integration
CONV
(HIGH at power-up)
CONV
(LOW at power-up)
Power Supplies
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
32
Power-On Initialization Period 50 µs
t
33
From Release Edge to Integration Start 50 µs
TABLE XI. Timing for the DDC112 Power-Up Sequence.
CLK = 10MHz CLK = 15MHz
SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS
t
30
1st Ncont Mode Data Ready (see SBAA024) 421.1 ±0.3 280.8 µs
t
31
2nd Ncont Mode Data Ready (see SBAA024) 454.8 303.2 µs
LAYOUT
Power Supplies and Grounding
Both AV
DD
and DV
DD
should be as quiet as possible. It is
particularly important to eliminate noise from AV
DD
that is
non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies for
AV
DD
and DV
DD
. In this case, each +5V supply of the
DDC112 should be bypassed with 10µF solid tantalum ca-
pacitors and 0.1µF ceramic capacitors. The second case
shows the DV
DD
power supply derived from the AV
DD
supply
with a < 10Ω isolation resistor. In both cases, the 0.1µF
capacitors should be placed as close to the DDC112 pack-
age as possible.
Shielding Analog Signal Paths
As with any precision circuit, careful printed circuit layout will
ensure the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—
particularly at the analog input pins. Digital signals should be
kept as far from the analog input signals as possible on the
PC board.