Datasheet

DDC112
21
SBAS085B
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FIGURE 20. Daisy-Chained DDC112s.
IN1
IN2
DCLK
DXMIT
DIN
DVALID
DOUT
DDC112
F”“E
Sensor F Sensor E
IN1
IN2
DCLK
DXMIT
DIN
DVALID
DOUT
DDC112
D”“C
Sensor D Sensor C
IN1
IN2
DCLK
DXMIT
DIN
DVALID
DOUT
Data Retrieval
Outputs
DDC112
B”“A
Sensor B Sensor A
R
P
R
P
R
P
Data Retrievel
Inputs
40 Bits 40 Bits 40 Bits
FIGURE 21. DDC112 in Parallel Operation.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
18
Propagation Delay from Rising Edge of CLK to DVALID LOW 30 ns
t
19
Propagation Delay from DXMIT LOW to DVALID HIGH 30 ns
t
20
Setup Time from DCLK LOW TO DXMIT LOW 20 ns
t
21
Propagation Delay from DXMIT LOW to Valid DOUT 30 ns
t
22
Hold Time that DOUT is Valid After Falling Edge of DCLK 5 ns
t
23
Propagation Delay from DXMIT HIGH to DOUT Disabled 30 ns
t
22A
(1)
Propagation Delay from Falling Edge of DCLK to Valid DOUT 25 ns
t
22B
(2)
Propagation Delay from Falling Edge of DCLK to Valid DOUT 30 ns
NOTES: (1) Applies to DDC112UK, YK only, with a maximum load of one DDC112UK, YK DIN (4pF typical) with an additional load of (5pF 100kΩ). (2) Applies
to DDC112U, Y only, with a maximum load of one DDC112U,Y DIN (4pF typical) with an additional load of (5pF 100kΩ).
FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112.
TABLE IX. Timing for the DDC112 Data Retrieval.
DIN
DIN
DIN
DOUT
DXMIT
DDC112
Data Output
DDC112
DDC112
Enable
DOUT
DXMIT
DOUT
DXMIT
t
18
t
19
t
20
t
21
t
22
t
23
Input 2
Bit 1
Input 2
Bit 20
Input 1
Bit 1
Input 1
Bit 20
MSB LSB MSB
Output Disabled
Output Enabled
Output Disabled
LSB
CLK
DVALID
DXMIT
DCLK
(1)
DOUT
NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.