Datasheet

DDC112
16
SBAS085B
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FIGURE 13. Non-Continuous Mode Timing.
Ncont Mode
Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (that is, sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being mea-
sured, reset and auto-zeroed. Before the DDC112 can
advance to states 3 or 6, both sides A and B must be
finished with the m/r/az cycle which takes time t
10
. When the
m/r/az cycles are completed, time t
11
is needed to prepare
the next side for integration. This time is required for the
ncont mode because the m/r/az cycle of the ncont mode is
slightly different from that of the cont mode. After the first
integration ends, DVALID
goes LOW in time t
8
. This is the
same time as in the cont mode. The second data will be
ready in time t
9
after the first data is ready. One result of the
naming convention used in this application bulletin is that
when the DDC112 is operating in the
ncont mode
, it passes
through both
ncont mode states
and
cont mode states
. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states.
Ncont mode
by definition means that for some portion of the time, neither
side A nor B is integrating. States that perform an integration
are labeled
cont mode states
while those that do not are
called
ncont mode states
. Since integrations are performed
in the ncont mode, just not continuously, some cont mode
states must be used in an ncont mode state pattern.
SYMBOL
DESCRIPTION VALUE (CLK = 10MHz) VALUE (CLK = 15MHz)
t
8
1st ncont mode data ready. 421.2 ±0.3µs 280.8 ±0.2µs
t
9
2nd ncont mode data ready. 454.8µs 303.2µs
t
10
Ncont mode m/r/az cycle. 910.8µs 607.2µs
t
11
Prepare side for integration. 24.0µs 24.0µs
23134 4 1 2
Int BInt AInt BInt A
m/r/az Bm/r/az A
m/r/az A m/r/az B
CONV
State
mbsy
m/r/az
Status
Integration
Status
DVALID
t
10
t
9
t
11
t
8
Side A
Data
Side B
Data
Side A
Data
Side B
Data