Datasheet

DDC112
15
SBAS085B
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determines the boundary between the cont and ncont modes
described earlier in the Overview section. DVALID
goes
LOW after CONV toggles in time t
7
, indicating that data is
ready to be retrieved. As shown in Figure 10, there are two
values for t
7
, depending on T
INT
. The reason for this will be
discussed in the Special Considerations section.
Figure 11 shows the result of inverting the logic level of
CONV. The only difference is in the first three states. After-
wards, the states toggle between 4 and 5 just as in the
previous example. Figure 12 shows the timing diagram of the
internal operations occurring during continuous mode opera-
tion.
FIGURE 11. Continuous Mode Timing (CONV LOW at power-up).
567845
Integrate AIntegrate B Integrate B Integrate A
m/r/az B m/r/az A m/r/az B
CONV
State
Integration
Status
m/r/az
Status
mbsy
DVALID
t
6
t
7
t = 0
Power-Up
Side B
Data
Side A
Data
Side B
Data
FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112.
t
12
t
12
t
14
t
13
T
INT
T
INT
End Integration Side A
Start Integration Side B
Side A
Side A
Data Ready
Side B
Data Ready
Side B
Side A Side B
Side A
End Integration Side B
Start Integration Side A
End Integration Side A
Start Integration Side B
CONV
DVALID
A/D Conversion
Input 1 (Internal)
A/D Conversion
Input 2 (Internal)
CLK = 10MHz CLK = 15MHz
SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS
T
INT
Integration Period (continuous mode) 500 1,000,000 333 1,000,000 µs
t
12
A/D Conversion Time (internally controlled) 202.2 134.8 µs
t
13
A/D Conversion Reset Time (internally controlled) 13.2 8.8 µs
t
14
Integrator and A/D Conversion Reset Time 61.8 41.2 µs
(internally controlled)
TABLE VI. Timing for the Internal Operation in the Continuous Mode.