Datasheet

®
DDC101
8
FIGURE 6. DATA TRANSMIT Timing Diagram.
FIGURE 4. Conversion Timing Diagrams.
Input
Range
Output
Format
SETUP In
DATA CLOCK
(4MHz, max for setup)
ACQ
LSB
t
5
RESET SETUP In
ACQ
MSB
Read Read Read Read
t
6
t
7
FIGURE 5. Input/Output Timing Diagram—SETUP Timing Diagram.
SYSTEM
CLOCK
DATA VALID
Out
DATA TRANSMIT
In
DATA OUTPUT
DATA CLOCK
(8MHz, max for data)
t
10
DDC(1)
Bit 1, MSB
DDC(n)
Bit 21, LSB
DDC
(n+1)
Bit 1
Output Disabled
Last DDC
Bit 21
Output Enabled
Output Disabled
t
12
Data can be read on rising or falling edge of Data Clock
DATA TRANSMIT In resets DATA VALID Out.
t
9
t
11
t
13
t
17
t
8
Continuous Integration Timing
Non-Continuous Integration Timing
SYSTEM
CLOCK
FDS In
Internal
Oversampling
Interval
Internal
Reset
SYSTEM
CLOCK
FDS In
Internal
Oversampling
Interval
Internal
Reset
FDS In should be coincident with negative clock.
FDS initiates oversampling period.
M Clock Periods
End of oversample period
initiates reset for next integration.
FDS In should be coincident with negative clock.
FDS initiates oversampling period.
End of FDS In
initiates end of Internal Reset.
End of oversample
period initiates
reset.
When Internal Reset period ends,
next integration begins.
DATA VALID
Out
t
2
t
1
t
3
DATA VALID Out
Next integration begins when 1 clock
period wide Internal Reset ends.
M Clock Periods
t
4
T
INT
'
T
INT