Datasheet

23
DDC101
®
Power Supplies
The ±5VDC supplies of the DDC101 should be bypassed
with 10µF solid tantalum capacitors and 0.1µF ceramic
capacitors. The supplies should each have a 10µF solid
tantalum capacitor at a central point on the PC board. Each
of the DDC101 power supply lines (V
S
+, V
S
–, V
DD
+) should
have a separate 0.1µF ceramic capacitor placed as close to
the DDC101 package as possible.
The digital power supply voltage, V
DD
+ must be equal to or
less than the analog power supply voltage, V
S
+. The analog
power supply, V
S
+, is connected to pins 5 and 6, these pins
should be hardwired together on the printed circuit board at
the pins for best performance.
V
DD
+ should be as quiet as possible with minimal noise
coupling. It is particularly important to eliminate noise from
V
DD
+ that is non-synchronous with DDC101 operation.
Figure 23 illustrates two acceptable ways to supply V
DD
+
power to the DDC101. The first case shows two separate
+5VDC supplies for V
DD
+ and V
S
+. The second case shows
the V
DD
+ power supply derived from the V
S
+ supply as used
on the DDC101 Evaluation Fixture Device Under Test
(DUT) board.
Oversampling Control
Samples/Integration—M - 4 bits
CODE SAMPLES PER INTEGRATION
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1XXX 256
SECTION 7
APPLICATIONS INFORMATION
BASIC PRINTED CIRCUIT BOARD LAYOUT
As with any precision circuit, careful printed circuit layout
will ensure best performance. Make short, direct intercon-
nections and avoid stray wiring capacitance—particularly at
the analog input pin. Digital signals should be kept as far
from the analog input signals as possible on the PC board.
Leakage currents between PC board traces can exceed the
input bias current of the DDC101 if care is not taken. A
circuit board “guard” pattern for the analog input pin and for
the PC board trace that connects to the analog input pin is
recommended. The guard pattern reduces leakage effects by
surrounding the analog input pin and trace with a low
impedance analog ground. Leakage currents from other
portions of the circuit will flow harmlessly to the low
impedance analog ground rather than into the analog input
of the DDC101. Analog ground pins are placed on either
side of the analog input pin in the DDC101 package to allow
convenient layout of guard patterns. Figure 22 illustrates the
use of guard patterns to protect the analog input.
Multiple Integration Control
Integrations/Conversion—L - 4 bits
CODE INTEGRATIONS PER CONVERSION
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1XXX 256
Input Range - 1 bit
CODE INPUT RANGE
0 Unipolar
1 Bipolar
Output Format - 1 bit
CODE OUTPUT FORMAT
1 Binary Two's Complement
0 Straight Binary
FIGURE 22. PC Board Layout Showing “Guard” Traces
Surrounding Analog Input Pin and Traces.
5
DDC101
6
12
0.1µF
0.1µF
10Ω
10µF
V
S
+
One +5VDC Suppl
y
5
DDC101
6
12
0.1µF
0.1µF
10µF
V
S
+
Separate +5VDC Supplies
10µF
V
DD
+
FIGURE 23. Positive Supply Connection Options.
DDC101
V
S
–
Guard
Pattern
Analog Common
Analog Input
Analog Common
Pin 1