Datasheet

 
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
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8
GENERATION OF DUAL POLARITY
VOLTAGES FROM TWO
SELF-SYNCHRONIZED DCR02s
Two DCR02s can be configured to produce a dual polarity
supply (that is, ±5 V); the circuit must be connected as
shown in Figure 5.
It should be observed that both DCR02s are positive
voltage regulators; therefore the ERROR
, ENABLE, and
V
REC
pins are relative to their respective devices, 0 V, and
must not be connected together.
PCB LAYOUT
RIPPLE AND NOISE
Careful consideration should be given to the layout of the
PCB in order for the best results to be obtained.
The DCR02 is a switching power supply and as such can
place high peak current demands on the input supply. In
order to avoid the supply falling momentarily during the
fast switching pulses, ground and power planes should be
used to track the power to the input of DCR02; this also
serves to reduce noise on the circuit. If this is not possible,
the supplies must be connected in a star formation, with
the tracks made as wide as possible.
If the SYNC pin is being used, the tracking between device
SYNC pins should be short, to avoid stray capacitance. If
the SYNC pin is not being used, it is advisable to place a
guard ring (connected to input ground) around this pin to
avoid any noise pickup.
The output should be taken from the device using ground
and power planes. This ensures minimum losses.
A good quality, low ESR ceramic capacitor placed as close
as practical across the input reduces reflected ripple and
ensure a smooth startup.
Additionally, a good quality, low ESR ceramic capacitor
placed as close as practical across the rectifier output
terminal and output ground also gives the best ripple and
noise performance.
THERMAL MANAGEMENT
Due to the high power density of this device, it is advisable
to provide a ground plane on the output. The output
regulator is mounted on a copper leadframe, and a ground
plane serves as an efficient heatsink.
DCR 02
V
OUT
V
IN
C
OUT
0.1
µ
F
C
FILTER
1
µ
F
V
POS
O/P
V
NEG
O/P
0V
ENABLE
V
REC
ERROR
V
S
U1
0V
SYNC
DCR 02
V
OUT
V
IN
C
OUT
0.1
µ
F
C
FILTER
1
µ
F
0V
ENABLE
V
REC
ERROR
V
S
U2
0V
SYNC
0V
C
IN
(1)
C
IN
(1)
NOTE: (1) Required 2.2
µ
F low ESR ceramic capacitor.
Figure 5. Dual Polarity Voltage Generation from Two Self-Synchronized DCR02s