Datasheet

OUTPUT RANGE
V V-
REFH REFL
262144
´ CODE BufferGain+V´
REFL
V
OUT
=
(1)
INPUT DATA FORMAT
POWER DOWN
HARDWARE RESET
DAC9881
SBAS438A MAY 2008 REVISED AUGUST 2008 .........................................................................................................................................................
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The maximum output range of the DAC9881 is V
REFL
to (V
REFH
V
REFL
) × G, where G is the output buffer gain
set by the GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin
is connected to IOV
DD
, the output buffer gain = 2. The output range must not be greater than AV
DD
; otherwise,
output saturation occurs. The DAC9881 output transfer function is given in Equation 1 :
Where:
CODE = 0 to 262143. This is the digital code loaded to the DAC.
Buffer Gain = 1 or 2 (set by the GAIN pin).
V
REFH
= reference high voltage applied to the device.
V
REFL
= reference low voltage applied to the device.
The USB/ BTC pin defines the input data format. When this pin is connected to IOV
DD
, the input data format is
straight binary, as shown in Table 1 . When this pin is connected to DGND, the input data format is twos
complement, as shown in Table 2 .
Table 1. Output vs Straight Binary Code
USB CODE 5V RANGE DESCRIPTION
3FFFFh +4.99998 +Full-Scale 1LSB
30000h +3.75000 3/4-Scale
20000h +2.50000 Midscale
10000h +1.25000 1/4-Scale
00000h 0.00000 Zero-Scale
Table 2. Output vs Twos Complement Code
BTC CODE 5V RANGE DESCRIPTION
1FFFFh +4.99998 +Full-Scale 1LSB
10000h +3.75000 3/4-Scale
00000h +2.50000 Midscale
3FFFFh +2.49998 Midscale 1LSB
30000h +1.25000 1/4-Scale
20000h 0.00000 Zero-Scale
The DAC9881 has a hardware power-down function. When the PDN pin is high, the device is in power-down
mode. When the device is in power-down, the V
OUT
pin is connected to ground through an internal 10k resistor,
but the contents of the input register and the DAC latch do not change and SPI communication remains active.
When the PDN pin returns low, the device returns to normal operation.
When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to
the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode, and the
input register and DAC latch maintain the reset value until new data are written.
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Product Folder Link(s): DAC9881